Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T76,T239,T240	Yes	T76,T239,T240	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T18,T182,T159	Yes	T18,T182,T159	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T182,T159	Yes	T18,T182,T159	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T186,T187,T74	Yes	T186,T187,T74	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T186,T187,T74	Yes	T186,T187,T74	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T6,T18,T63	Yes	T6,T18,T63	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T54,T67,T77	Yes	T54,T67,T77	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T54,T67,T77	Yes	T54,T67,T77	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T54,T67,T77	Yes	T54,T67,T77	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T54,T67,T77	Yes	T54,T67,T77	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T54,T146,T147	Yes	T54,T146,T147	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T54,T67,T77	Yes	T54,T67,T77	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T54,T67,T77	Yes	T54,T67,T77	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T10,T75,T79	Yes	T10,T75,T79	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T10,T75,*T76	Yes	T10,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T10,T75,*T76	Yes	T10,T75,T76	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T78	Yes	T75,T76,T79	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T10,*T75,*T76	Yes	T10,T75,T76	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T10,T75,T76	Yes	T10,T75,T76	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T67,*T105,*T77	Yes	T67,T105,T77	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T67,*T105,*T77	Yes	T67,T105,T77	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T6,T18	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T67,T105,T77	Yes	T67,T105,T77	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T51,T52,T64	Yes	T51,T52,T64	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T51,T52,T53	Yes	T51,T52,T53	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T57,T10,T58	Yes	T57,T10,T58	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T19,T57,T415	Yes	T19,T57,T415	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T19,T57,T415	Yes	T19,T57,T415	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T57,T10,T58	Yes	T57,T10,T58	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T19,T57,T415	Yes	T19,T57,T415	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T10,*T75,*T76	Yes	T10,T75,T76	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T19,T57,T415	Yes	T19,T57,T415	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T19,T57,T415	Yes	T19,T57,T415	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T75,T76,T78	Yes	T75,T76,T79	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T19,T415,T267	Yes	T19,T415,T267	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T75,T76	Yes	T57,T10,T58	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T19,T415,T267	Yes	T19,T57,T415	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T10,T75,T76	Yes	T10,T75,T76	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T78	Yes	T75,T76,T79	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T19,*T416,*T267	Yes	T19,T415,T416	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T19,T57,T415	Yes	T19,T57,T415	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T6,T63,T182	Yes	T6,T63,T182	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T78	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T24,T198,T25	Yes	T24,T198,T25	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T149,T24,T198	Yes	T57,T149,T24	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T24,T198,T25	Yes	T24,T198,T25	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T78	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T78	Yes	T75,T76,T79	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T24,*T198,*T307	Yes	T24,T198,T307	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T57,T149,T24	Yes	T57,T149,T24	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T57,T198,T307	Yes	T57,T198,T307	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T57,T198,T42	Yes	T57,T198,T42	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T198,T307	Yes	T57,T198,T307	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T57,T198,T307	Yes	T57,T198,T307	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T57,T198,T42	Yes	T57,T198,T42	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T57,T198,T307	Yes	T57,T198,T307	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T57,T198,T307	Yes	T57,T198,T307	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T57,T198,T307	Yes	T57,T198,T307	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T198,T42,T150	Yes	T198,T42,T150	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T198,T307,T42	Yes	T57,T198,T307	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T198,T42,T150	Yes	T198,T42,T150	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T74,T75,T76	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T198,*T307,*T42	Yes	T198,T307,T42	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T57,T198,T307	Yes	T57,T198,T307	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T54,*T75,*T78	Yes	T54,T75,T78	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T75,T78,T79	Yes	T75,T78,T79	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T75,T78,T79	Yes	T75,T78,T79	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	INPUT
tl_usbdev_i.d_error	Yes	Yes	T75,T78,T79	Yes	T75,T78,T79	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T54,T198,T402	Yes	T54,T198,T402	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T198,T402	Yes	T54,T198,T402	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T54,T57,T198	Yes	T54,T198,T1	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T75,T78,T79	Yes	T75,T78,T79	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T78	Yes	T54,T75,T78	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T75,T78,T79	Yes	T75,T78,T79	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T54,*T57,*T198	Yes	T54,T198,T1	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T54,T57,T198	Yes	T54,T57,T198	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T74,T75,T79	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T74,T75	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T10,T74,T75	Yes	T10,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T10,T74,T75	Yes	T10,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T10,T74,T75	Yes	T10,T74,T75	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T51,T714,T57	Yes	T51,T714,T57	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T714,T57	Yes	T51,T714,T57	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T51,T714,T165	Yes	T51,T714,T165	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T51,T714,T57	Yes	T51,T714,T57	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T51,T714,T165	Yes	T51,T714,T165	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T10,*T75,*T76	Yes	T10,T75,T76	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T714,T325,T715	Yes	T714,T325,T715	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T51,T714,T165	Yes	T51,T714,T165	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T51,T714,T165	Yes	T51,T714,T165	INPUT
tl_hmac_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T51,T714,T165	Yes	T51,T714,T165	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T714,T165	Yes	T51,T714,T165	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T51,T714,T57	Yes	T51,T714,T52	INPUT
tl_hmac_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T10,*T75,*T76	Yes	T10,T75,T76	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T51,*T714,*T57	Yes	T51,T714,T52	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T51,T714,T165	Yes	T51,T714,T165	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T85,T86,T57	Yes	T85,T86,T57	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T85,T86,T165	Yes	T85,T86,T165	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T85,T86,T165	Yes	T85,T86,T165	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T85,T86,T57	Yes	T85,T86,T57	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T85,T86,T165	Yes	T85,T86,T165	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T56,*T10,*T75	Yes	T56,T10,T75	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T86,T463,T464	Yes	T86,T463,T464	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T85,T86,T165	Yes	T85,T86,T165	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T85,T86,T165	Yes	T85,T86,T165	INPUT
tl_kmac_i.d_error	Yes	Yes	T74,T75,T76	Yes	T75,T76,T78	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T85,T86,T165	Yes	T85,T86,T165	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T86,T165	Yes	T85,T86,T165	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T85,T86,T57	Yes	T86,T463,T464	INPUT
tl_kmac_i.d_sink	Yes	Yes	T75,T76,T78	Yes	T74,T75,T76	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T56,*T10,*T75	Yes	T56,T10,T74	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T75,T76,T78	Yes	T74,T75,T76	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T85,*T86,*T57	Yes	T86,T463,T464	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T85,T86,T165	Yes	T85,T86,T165	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T54,T57,T285	Yes	T54,T57,T285	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T57,T285	Yes	T54,T57,T285	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T165,T54,T57	Yes	T165,T54,T57	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T54,T57,T285	Yes	T54,T57,T285	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T165,T54,T57	Yes	T165,T54,T57	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T75,T79	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T165,T54,T57	Yes	T165,T54,T57	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T165,T54,T57	Yes	T165,T54,T57	INPUT
tl_aes_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T165,T54,T285	Yes	T165,T54,T285	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T285,T108	Yes	T54,T57,T285	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T165,T54,T285	Yes	T165,T54,T57	INPUT
tl_aes_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T76	Yes	T54,T75,T76	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T165,*T54,*T285	Yes	T165,T54,T285	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T165,T54,T57	Yes	T165,T54,T57	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T10,*T75,*T79	Yes	T10,T75,T79	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T85,T87,T121	Yes	T85,T87,T121	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T10,*T75,*T79	Yes	T10,T75,T79	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T79,T249	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T85,*T87,*T121	Yes	T51,T85,T87	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T85,T87,T54	Yes	T85,T87,T54	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T54,*T10,*T75	Yes	T54,T10,T75	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T85,T87,T54	Yes	T85,T87,T54	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T54,*T10,*T75	Yes	T54,T10,T75	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T85,*T87,*T54	Yes	T85,T87,T54	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T74,T75	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T74,T75,T79	Yes	T74,T75,T79	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T85,T87,T121	Yes	T85,T87,T121	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T74,T75,T79	Yes	T74,T75,T79	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T74,T75	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T79	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T85,*T87,*T121	Yes	T85,T87,T121	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T10,*T75,*T79	Yes	T10,T75,T79	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	INPUT
tl_edn1_i.d_error	Yes	Yes	T75,T79,T249	Yes	T74,T75,T79	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T85,T87,T121	Yes	T85,T87,T121	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T87,T121	Yes	T85,T87,T57	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T85,T87,T121	Yes	T85,T87,T57	INPUT
tl_edn1_i.d_sink	Yes	Yes	T74,T75,T79	Yes	T75,T79,T249	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T75,T79	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T85,*T87,*T121	Yes	T85,T87,T121	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T85,T87,T57	Yes	T85,T87,T57	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T75,*T79,*T249	Yes	T75,T79,T249	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T51,T87,T57	Yes	T51,T87,T57	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T87,T165	Yes	T51,T87,T165	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T51,T87,T165	Yes	T51,T87,T165	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T51,T87,T57	Yes	T51,T87,T57	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T51,T87,T165	Yes	T51,T87,T165	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T56,*T186,*T187	Yes	T56,T186,T187	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T51,T87,T165	Yes	T51,T87,T165	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T51,T87,T165	Yes	T51,T87,T165	INPUT
tl_otbn_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T51,T87,T173	Yes	T51,T87,T173	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T87,T173	Yes	T51,T87,T173	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T51,T87,T57	Yes	T51,T87,T173	INPUT
tl_otbn_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T56,*T186,*T187	Yes	T56,T186,T187	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T51,*T87,*T57	Yes	T51,T87,T173	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T51,T87,T57	Yes	T51,T87,T57	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T51,T85,T57	Yes	T51,T85,T57	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T85,T57	Yes	T51,T85,T57	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T51,T85,T57	Yes	T51,T85,T57	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T51,T85,T57	Yes	T51,T85,T57	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T51,T85,T57	Yes	T51,T85,T57	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T10,*T75,*T76	Yes	T10,T75,T76	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T51,T85,T57	Yes	T51,T85,T57	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T51,T85,T57	Yes	T51,T85,T57	INPUT
tl_keymgr_i.d_error	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T85,T68,T206	Yes	T85,T68,T206	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T85,T52	Yes	T51,T85,T57	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T51,T85,T52	Yes	T51,T85,T57	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T75,T76	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T51,*T85,*T52	Yes	T51,T85,T52	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T51,T85,T57	Yes	T51,T85,T57	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T10,*T75,*T76	Yes	T10,T75,T76	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T10,T75,T79	Yes	T10,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T74,T75,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T10,*T74,*T75	Yes	T10,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T75,T78,T79	Yes	T75,T76,T79	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T399,*T456,*T74	Yes	T399,T456,T74	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T74,T75,T79	Yes	T74,T75,T79	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T303,T304,T305	Yes	T303,T304,T305	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T112,T276,T277	Yes	T51,T57,T52	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T112,T276,T277	Yes	T51,T57,T52	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T74,T75,T79	Yes	T74,T75,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T79	Yes	T399,T456,T74	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T74,T75,T79	Yes	T74,T75,T79	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T112,*T276,*T277	Yes	T457,T112,T276	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range