dashboard | hierarchy | modlist | groups | tests | asserts

Module Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[1].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[2].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67 50.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67 50.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[5].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67 50.00 50.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67 50.00 50.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[8].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[9].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[10].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[11].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[12].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[13].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[14].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[15].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[16].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[17].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[18].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[19].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[20].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_dio_pads[21].u_dio_pad


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT30,T60,T72
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT1,T2,T30
01CoveredT39,T40,T41
10CoveredT4,T5,T6
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T41,T174
11CoveredT30,T34,T35

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T30
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT30,T34,T35

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T41,T174
11CoveredT30,T34,T35

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T41,T174

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT30,T34,T35
11CoveredT39,T41,T174

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T34,T35
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T39,T41,T174
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[1].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT30,T60,T72
10CoveredT39,T41,T174
11CoveredT39,T41,T174

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT30,T60,T72
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT30,T34,T21

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT30,T34,T21

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT41,T174,T175
11CoveredT30,T34,T21

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT41,T174,T175

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT30,T34,T21
11CoveredT41,T174,T175

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T30,T34,T21
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T41,T174,T175
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[2].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3900
CONT_ASSIGN51100.00
CONT_ASSIGN10200
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 0 1
102 unreachable
114 1 1
115 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions4250.00
Logical4250.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10Not Covered
11CoveredT4,T5,T6

 LINE       114
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 114 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 114 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Not Covered


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[5].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL3266.67
CONT_ASSIGN3900
CONT_ASSIGN51100.00
CONT_ASSIGN10200
CONT_ASSIGN11411100.00
CONT_ASSIGN11511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 0 1
102 unreachable
114 1 1
115 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions4250.00
Logical4250.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10Not Covered
11CoveredT4,T5,T6

 LINE       114
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0Not Covered
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 1 50.00
TERNARY 114 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 114 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Not Covered


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[8].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT54,T24,T25
01CoveredT24,T25,T26
10CoveredT39,T41,T174
11CoveredT39,T41,T174

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT41,T174,T175
11CoveredT24,T25,T26

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT41,T174,T175

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT41,T174,T175

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT41,T174,T175
11CoveredT24,T25,T26

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T41,T174,T175
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[9].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT54,T24,T25
01CoveredT24,T25,T26
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T39,T40

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT21,T39,T40
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT21,T39,T40

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT21,T39,T40

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T21,T39,T40
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[10].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT54,T24,T25
01CoveredT24,T25,T26
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT22,T23,T39

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT40,T41,T174

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT22,T23,T39
11CoveredT40,T41,T174

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT22,T23,T39

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT40,T41,T174
11CoveredT22,T23,T39

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T40,T41,T174
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T22,T23,T39
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[11].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT54,T24,T25
01CoveredT24,T25,T26
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[12].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT54,T24,T25
01CoveredT24,T25,T26
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT24,T25,T26

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT24,T25,T26

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT42,T43,T44

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[13].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT54,T24,T25
01CoveredT24,T25,T26
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT24,T25,T26
01CoveredT39,T40,T41
10CoveredT4,T5,T6
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T41,T174
11CoveredT24,T25,T26

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT24,T25,T26
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT24,T25,T26

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT42,T43,T44

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T42,T43,T44
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[14].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT24,T48,T138
01CoveredT24,T48,T138
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT24,T25,T26

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT24,T25,T26

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[15].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT24,T48,T138
01CoveredT24,T48,T138
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T48,T138
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT24,T48,T138

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT40,T41,T175

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT24,T48,T138
11CoveredT40,T41,T175

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T48,T138

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT40,T41,T175
11CoveredT24,T48,T138

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T40,T41,T175
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T24,T48,T138
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[16].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT24,T48,T138
01CoveredT24,T25,T26
10CoveredT39,T41,T174
11CoveredT39,T41,T174

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT24,T25,T26

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT40,T41,T174

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT40,T41,T174

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT40,T41,T174
11CoveredT24,T25,T26

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T40,T41,T174
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[17].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT24,T48,T138
01CoveredT24,T25,T26
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT24,T25,T26

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT39,T40,T41

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT40,T41,T174

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT24,T25,T26
11CoveredT40,T41,T174

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT24,T25,T26

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT40,T41,T174
11CoveredT24,T25,T26

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T40,T41,T174
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T24,T25,T26
0 Covered T4,T5,T6


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[18].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN5700
CONT_ASSIGN6411100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
57 unreachable
64 1 1
66 1 1
71 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       64
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       66
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT24,T48,T138
10CoveredT41,T174,T175
11CoveredT40,T41,T174

 LINE       71
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 64 2 2 100.00
TERNARY 71 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 71 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[19].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN5700
CONT_ASSIGN6411100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
57 unreachable
64 1 1
66 1 1
71 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       64
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       66
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT24,T138,T188
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       71
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
TERNARY 64 2 2 100.00
TERNARY 71 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 64 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 71 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[20].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

Line Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN3900
CONT_ASSIGN5111100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
39 unreachable
51 1 1
78 1 1
80 1 1
84 1 1
85 1 1
92 1 1
93 1 1
95 1 1


Cond Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions3333100.00
Logical3333100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------
-1--2-StatusTests
01Unreachable
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1
-1-StatusTests
0CoveredT39,T40,T41
1CoveredT4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT190,T31,T32
10CoveredT39,T40,T41
11CoveredT39,T40,T41

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT39,T40,T41
10CoveredT31,T32,T33
11CoveredT39,T40,T41

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------
-1--2-StatusTests
01CoveredT13,T14,T15
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------
-1--2-StatusTests
00CoveredT39,T40,T41
01CoveredT4,T5,T6
10CoveredT45,T46,T47

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT39,T40,T41
11CoveredT45,T46,T47

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------
-1--2-StatusTests
01CoveredT39,T40,T41
10CoveredT4,T5,T6
11CoveredT39,T40,T41

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT13,T14,T15
1CoveredT4,T5,T6

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------
-1--2-StatusTests
01CoveredT13,T14,T15
10CoveredT39,T40,T41
11CoveredT4,T5,T6

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT39,T40,T41

Branch Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 78 2 2 100.00
TERNARY 92 2 2 100.00
TERNARY 93 2 2 100.00
TERNARY 95 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 78 (ie) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T39,T40,T41


LineNo. Expression -1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


LineNo. Expression -1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T13,T14,T15


LineNo. Expression -1-: 95 (attr_i.pull_en) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T41
0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_padring.gen_dio_pads[21].u_dio_pad.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AnalogNoScan_A 983 983 0 0


AnalogNoScan_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 983 983 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T18 1 1 0 0
T51 1 1 0 0
T85 1 1 0 0
T86 1 1 0 0
T87 1 1 0 0
T88 1 1 0 0
T89 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%