Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T6,T63,T182	Yes	T6,T63,T182	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_uart0_i.d_error	Yes	Yes	T74,T75,T79	Yes	T75,T76,T79	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T113,T54,T205	Yes	T113,T54,T205	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_uart0_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T74,T75	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T4,*T51,*T113	Yes	T4,T51,T113	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T4,T51,T113	Yes	T4,T51,T113	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_uart1_i.d_error	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T54,T200,T115	Yes	T54,T200,T115	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T149,T200	Yes	T54,T57,T149	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T54,T149,T200	Yes	T54,T57,T149	INPUT
tl_uart1_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T74,T75	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T54,*T200,*T115	Yes	T54,T200,T115	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T54,T142,T143	Yes	T54,T142,T143	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T54,T142,T143	Yes	T54,T142,T143	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_uart2_i.d_error	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T54,T142,T143	Yes	T54,T142,T143	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T149,T142	Yes	T54,T57,T149	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T54,T149,T142	Yes	T54,T57,T149	INPUT
tl_uart2_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T74,T75	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T75,T76,T79	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T54,*T142,*T143	Yes	T54,T142,T143	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T54,T28,T29	Yes	T54,T28,T29	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T54,T28,T29	Yes	T54,T28,T29	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_uart3_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T54,T28,T29	Yes	T54,T28,T29	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T149,T28	Yes	T54,T57,T149	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T54,T149,T28	Yes	T54,T57,T149	INPUT
tl_uart3_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T79,T249	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T75,T76	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T54,*T28,*T29	Yes	T54,T28,T29	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T54,T57,T149	Yes	T54,T57,T149	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T198,T321,T340	Yes	T198,T321,T340	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T198,T321,T340	Yes	T198,T321,T340	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T57,T149,T198	Yes	T57,T149,T198	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T57,T149,T198	Yes	T57,T149,T198	INPUT
tl_i2c0_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T321,T340,T324	Yes	T321,T340,T324	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T149,T198,T321	Yes	T57,T149,T198	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T149,T198,T321	Yes	T57,T149,T198	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T10,*T75,*T79	Yes	T10,T75,T76	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T198,*T321,*T340	Yes	T198,T321,T340	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T57,T149,T198	Yes	T57,T149,T198	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T89,T198,T321	Yes	T89,T198,T321	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T89,T198,T321	Yes	T89,T198,T321	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T89,T57,T149	Yes	T89,T57,T149	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T89,T57,T149	Yes	T89,T57,T149	INPUT
tl_i2c1_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T89,T321,T341	Yes	T89,T321,T341	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T89,T149,T198	Yes	T89,T57,T149	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T89,T149,T198	Yes	T89,T57,T149	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T10,*T75,*T79	Yes	T10,T75,T79	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T89,*T198,*T321	Yes	T89,T198,T321	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T89,T57,T149	Yes	T89,T57,T149	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T203,T198,T321	Yes	T203,T198,T321	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T203,T198,T321	Yes	T203,T198,T321	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T57,T149,T203	Yes	T57,T149,T203	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T57,T149,T203	Yes	T57,T149,T203	INPUT
tl_i2c2_i.d_error	Yes	Yes	T75,T76,T79	Yes	T74,T75,T76	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T203,T321,T336	Yes	T203,T321,T336	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T149,T203,T198	Yes	T57,T149,T203	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T149,T203,T198	Yes	T57,T149,T203	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T79,T249	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T10,*T75,*T76	Yes	T10,T75,T79	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T74,T75,T79	Yes	T75,T79,T249	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T203,*T198,*T321	Yes	T203,T198,T321	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T57,T149,T203	Yes	T57,T149,T203	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T204,T353,T354	Yes	T204,T353,T354	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T204,T353,T354	Yes	T204,T353,T354	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T57,T204,T353	Yes	T57,T204,T353	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T57,T204,T353	Yes	T57,T204,T353	INPUT
tl_pattgen_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T204,T353,T354	Yes	T204,T353,T354	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T204,T353,T354	Yes	T57,T204,T353	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T204,T353,T354	Yes	T57,T204,T353	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T56,T75,T76	Yes	T56,T75,T76	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T204,*T353,*T354	Yes	T204,T353,T354	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T57,T204,T353	Yes	T57,T204,T353	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T61,T202,T713	Yes	T61,T202,T713	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T61,T202,T713	Yes	T61,T202,T713	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T61,T57,T202	Yes	T61,T57,T202	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T61,T57,T202	Yes	T61,T57,T202	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T61,T202,T713	Yes	T61,T202,T713	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T61,T202,T713	Yes	T61,T57,T202	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T61,T202,T713	Yes	T61,T57,T202	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T75,T76,T78	Yes	T75,T76,T79	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T10,T75,*T79	Yes	T10,T75,T76	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T61,*T202,*T713	Yes	T61,T202,T713	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T61,T57,T202	Yes	T61,T57,T202	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T27,T321,T36	Yes	T27,T321,T36	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T321,T36	Yes	T27,T57,T321	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T27,T321,T36	Yes	T27,T57,T321	INPUT
tl_gpio_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T10,*T75,*T79	Yes	T10,T75,T76	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T18	Yes	T4,T5,T6	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T24,T198,T48	Yes	T24,T198,T48	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T24,T198,T48	Yes	T24,T198,T48	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T57,T24,T198	Yes	T57,T24,T198	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T57,T24,T198	Yes	T57,T24,T198	INPUT
tl_spi_device_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T24,T198,T48	Yes	T24,T198,T48	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T24,T198,T48	Yes	T24,T198,T48	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T57,T24,T198	Yes	T24,T198,T48	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T75,*T76,*T79	Yes	T75,T76,T79	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T57,*T24,*T198	Yes	T24,T198,T48	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T57,T24,T198	Yes	T57,T24,T198	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T244,T245,T730	Yes	T244,T245,T730	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T244,T245,T730	Yes	T244,T245,T730	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T57,T244,T245	Yes	T57,T244,T245	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T57,T244,T245	Yes	T57,T244,T245	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T244,T245,T730	Yes	T244,T245,T730	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T244,T245,T730	Yes	T57,T244,T245	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T244,T245,T730	Yes	T57,T244,T245	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T249	Yes	T75,T79,T249	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T79,T249	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T244,*T245,*T730	Yes	T244,T245,T730	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T57,T244,T245	Yes	T57,T244,T245	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T51,T88,T61	Yes	T51,T88,T61	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T51,T88,T61	Yes	T51,T88,T61	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T51,T88,T61	Yes	T51,T88,T61	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T51,T88,T61	Yes	T51,T88,T61	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T51,T61,T165	Yes	T51,T61,T165	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T51,T61,T165	Yes	T51,T61,T165	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T51,T61,T165	Yes	T51,T61,T165	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T10,*T75,*T79	Yes	T10,T75,T76	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T51,*T61,*T165	Yes	T51,T88,T61	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T51,T88,T61	Yes	T51,T88,T61	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T74,T75,T76	Yes	T75,T76,T78	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T10,*T75,*T78	Yes	T10,T75,T76	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T78	Yes	T74,T75,T76	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T86,T88,T113	Yes	T86,T88,T113	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T85,T86,T88	Yes	T85,T86,T88	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T74,T75,T79	Yes	T74,T75,T76	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T86,T88,T113	Yes	T86,T88,T113	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T74,T75,T79	Yes	T74,T75,T76	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T54,*T74,*T75	Yes	T54,T74,T75	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T79	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T86,*T88,*T113	Yes	T86,T88,T113	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T75,T76,T78	Yes	T75,T76,T79	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T56,*T10,*T75	Yes	T56,T10,T75	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T75,T78,T79	Yes	T75,T78,T79	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T146,*T147,*T148	Yes	T146,T147,T148	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T75,T76,T78	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T85,*T55,*T57	Yes	T85,T55,T149	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T56,T75,T76	Yes	T56,T75,T76	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T56,T75,T76	Yes	T56,T75,T76	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T56,T75,T76	Yes	T56,T75,T76	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T56,T75,T76	Yes	T56,T75,T76	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T56,T75,T76	Yes	T56,T75,T76	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T56,T75,T76	Yes	T56,T75,T76	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T6,T18	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T56,T75,T76	Yes	T56,T75,T76	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T51,T113,T19	Yes	T51,T113,T19	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T51,T113,T19	Yes	T51,T113,T19	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T51,T113,T19	Yes	T51,T113,T19	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T51,T113,T19	Yes	T51,T113,T19	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T51,T20,T55	Yes	T51,T20,T55	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T55,T62	Yes	T20,T55,T57	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T51,T19,T20	Yes	T51,T113,T19	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T67,*T77,*T56	Yes	T67,T77,T56	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T19,*T20,*T55	Yes	T51,T113,T19	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T51,T113,T19	Yes	T51,T113,T19	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T53,T122,T96	Yes	T53,T122,T96	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T122,T96	Yes	T57,T53,T122	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T75,*T79,*T249	Yes	T75,T76,T79	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T18	Yes	T4,T5,T6	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T75,T76	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T78	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T6,*T18,*T63	Yes	T6,T18,T51	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T51,T52,T117	Yes	T51,T52,T117	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T51,T52,T117	Yes	T51,T52,T117	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T117,T112,T169	Yes	T117,T112,T169	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T117,T112,T169	Yes	T51,T57,T52	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T117,T112,T169	Yes	T51,T57,T52	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T75,*T78,*T79	Yes	T75,T76,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T117,*T112,*T169	Yes	T117,T457,T112	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T51,T57,T52	Yes	T51,T57,T52	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T5,T6,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T6,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T5,T6,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T78	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T186,*T187,*T458	Yes	T186,T187,T458	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T74,T75,T78	Yes	T74,T75,T78	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T18,T63	Yes	T6,T18,T63	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T399,T75	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T76,T79	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T6,*T18,*T51	Yes	T6,T18,T51	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T6,T18,T51	Yes	T6,T18,T51	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T54,T45,T190	Yes	T54,T45,T190	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T54,T45,T190	Yes	T54,T45,T190	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T54,T57,T45	Yes	T54,T57,T45	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T54,T57,T45	Yes	T54,T57,T45	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T75,T79,T249	Yes	T75,T79,T249	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T54,T45,T190	Yes	T54,T45,T190	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T45,T190	Yes	T54,T57,T45	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T54,T45,T190	Yes	T54,T57,T45	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T75,T79,T249	Yes	T75,T76,T79	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T79	Yes	T54,T75,T76	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T79	Yes	T75,T79,T249	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T54,*T45,*T190	Yes	T54,T45,T190	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T54,T57,T45	Yes	T54,T57,T45	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T54,T7,T95	Yes	T54,T7,T95	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T54,T7,T95	Yes	T54,T7,T95	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T54,T57,T7	Yes	T54,T57,T7	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T54,T57,T7	Yes	T54,T57,T7	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T75,T76,T78	Yes	T75,T78,T79	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T54,T95,T1	Yes	T54,T7,T95	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T7,T95	Yes	T54,T57,T7	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T54,T7,T95	Yes	T54,T57,T7	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T54,*T75,*T78	Yes	T54,T75,T76	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T54,*T95,*T1	Yes	T54,T7,T95	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T54,T57,T7	Yes	T54,T57,T7	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T54,*T67,*T77	Yes	T54,T67,T77	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T54,T56,T10	Yes	T54,T56,T10	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T75,T76,T78	Yes	T75,T76,T78	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T75,T78,T79	Yes	T75,T76,T78	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T75,T78,T79	Yes	T75,T78,T79	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T75,*T76,*T78	Yes	T75,T76,T78	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range