Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T171,T172,T296
0	1	Covered	T171,T172,T296
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T171,T172,T296
1	Covered	T171,T172,T296

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T171,T172,T296
1	Covered	T171,T172,T296

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T171,T172,T296
1	1	Covered	T171,T172,T296

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T171,T172,T296
1	0	Covered	T171,T172,T296
1	1	Covered	T171,T172,T296

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T171,T172,T296

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T171,T172,T296
0	Covered	T171,T172,T296

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T171,T172,T296
0	Covered	T171,T172,T296

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	946033276	928570952	0	0
CheckNGreaterZero_A	1966	1966	0	0
GntImpliesReady_A	946033276	8380	0	0
GntImpliesValid_A	946033276	8380	0	0
GrantKnown_A	946033276	928570952	0	0
IdxKnown_A	946033276	928570952	0	0
IndexIsCorrect_A	946033276	8380	0	0
NoReadyValidNoGrant_A	946033276	0	0	0
Priority_A	946033276	8380	0	0
ReadyAndValidImplyGrant_A	946033276	8380	0	0
ReqAndReadyImplyGrant_A	946033276	8380	0	0
ReqImpliesValid_A	946033276	8380	0	0
ValidKnown_A	946033276	928570952	0	0
gen_data_port_assertion.DataFlow_A	946033276	8380	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	928570952	0	0
T4	150776	150660	0	0
T5	398168	397838	0	0
T6	458388	458148	0	0
T18	448366	448134	0	0
T51	261076	261064	0	0
T85	761022	760802	0	0
T86	176906	176804	0	0
T87	757704	757594	0	0
T88	308898	308788	0	0
T89	697312	697188	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1966	1966	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T18	2	2	0	0
T51	2	2	0	0
T85	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0
T89	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	8380	0	0
T82	1024028	0	0	0
T144	703344	0	0	0
T166	100260	0	0	0
T171	153816	2790	0	0
T172	0	2793	0	0
T191	206924	0	0	0
T296	0	2797	0	0
T405	296516	0	0	0
T406	551778	0	0	0
T407	179522	0	0	0
T408	309412	0	0	0
T409	124224	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	8380	0	0
T82	1024028	0	0	0
T144	703344	0	0	0
T166	100260	0	0	0
T171	153816	2790	0	0
T172	0	2793	0	0
T191	206924	0	0	0
T296	0	2797	0	0
T405	296516	0	0	0
T406	551778	0	0	0
T407	179522	0	0	0
T408	309412	0	0	0
T409	124224	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	928570952	0	0
T4	150776	150660	0	0
T5	398168	397838	0	0
T6	458388	458148	0	0
T18	448366	448134	0	0
T51	261076	261064	0	0
T85	761022	760802	0	0
T86	176906	176804	0	0
T87	757704	757594	0	0
T88	308898	308788	0	0
T89	697312	697188	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	928570952	0	0
T4	150776	150660	0	0
T5	398168	397838	0	0
T6	458388	458148	0	0
T18	448366	448134	0	0
T51	261076	261064	0	0
T85	761022	760802	0	0
T86	176906	176804	0	0
T87	757704	757594	0	0
T88	308898	308788	0	0
T89	697312	697188	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	8380	0	0
T82	1024028	0	0	0
T144	703344	0	0	0
T166	100260	0	0	0
T171	153816	2790	0	0
T172	0	2793	0	0
T191	206924	0	0	0
T296	0	2797	0	0
T405	296516	0	0	0
T406	551778	0	0	0
T407	179522	0	0	0
T408	309412	0	0	0
T409	124224	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	8380	0	0
T82	1024028	0	0	0
T144	703344	0	0	0
T166	100260	0	0	0
T171	153816	2790	0	0
T172	0	2793	0	0
T191	206924	0	0	0
T296	0	2797	0	0
T405	296516	0	0	0
T406	551778	0	0	0
T407	179522	0	0	0
T408	309412	0	0	0
T409	124224	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	8380	0	0
T82	1024028	0	0	0
T144	703344	0	0	0
T166	100260	0	0	0
T171	153816	2790	0	0
T172	0	2793	0	0
T191	206924	0	0	0
T296	0	2797	0	0
T405	296516	0	0	0
T406	551778	0	0	0
T407	179522	0	0	0
T408	309412	0	0	0
T409	124224	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	8380	0	0
T82	1024028	0	0	0
T144	703344	0	0	0
T166	100260	0	0	0
T171	153816	2790	0	0
T172	0	2793	0	0
T191	206924	0	0	0
T296	0	2797	0	0
T405	296516	0	0	0
T406	551778	0	0	0
T407	179522	0	0	0
T408	309412	0	0	0
T409	124224	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	8380	0	0
T82	1024028	0	0	0
T144	703344	0	0	0
T166	100260	0	0	0
T171	153816	2790	0	0
T172	0	2793	0	0
T191	206924	0	0	0
T296	0	2797	0	0
T405	296516	0	0	0
T406	551778	0	0	0
T407	179522	0	0	0
T408	309412	0	0	0
T409	124224	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	928570952	0	0
T4	150776	150660	0	0
T5	398168	397838	0	0
T6	458388	458148	0	0
T18	448366	448134	0	0
T51	261076	261064	0	0
T85	761022	760802	0	0
T86	176906	176804	0	0
T87	757704	757594	0	0
T88	308898	308788	0	0
T89	697312	697188	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	946033276	8380	0	0
T82	1024028	0	0	0
T144	703344	0	0	0
T166	100260	0	0	0
T171	153816	2790	0	0
T172	0	2793	0	0
T191	206924	0	0	0
T296	0	2797	0	0
T405	296516	0	0	0
T406	551778	0	0	0
T407	179522	0	0	0
T408	309412	0	0	0
T409	124224	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T171,T172,T296
0	1	Covered	T171,T172,T296
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T171,T172,T296
1	Covered	T171,T172,T296

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T171,T172,T296
1	Covered	T171,T172,T296

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T171,T172,T296
1	1	Covered	T171,T172,T296

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T171,T172,T296
1	0	Covered	T171,T172,T296
1	1	Covered	T171,T172,T296

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T171,T172,T296

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T171,T172,T296
0	Covered	T171,T172,T296

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T171,T172,T296
0	Covered	T171,T172,T296

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	473016638	464285476	0	0
CheckNGreaterZero_A	983	983	0	0
GntImpliesReady_A	473016638	5190	0	0
GntImpliesValid_A	473016638	5190	0	0
GrantKnown_A	473016638	464285476	0	0
IdxKnown_A	473016638	464285476	0	0
IndexIsCorrect_A	473016638	5190	0	0
NoReadyValidNoGrant_A	473016638	0	0	0
Priority_A	473016638	5190	0	0
ReadyAndValidImplyGrant_A	473016638	5190	0	0
ReqAndReadyImplyGrant_A	473016638	5190	0	0
ReqImpliesValid_A	473016638	5190	0	0
ValidKnown_A	473016638	464285476	0	0
gen_data_port_assertion.DataFlow_A	473016638	5190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	464285476	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	5190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1726	0	0
T172	0	1730	0	0
T191	103462	0	0	0
T296	0	1734	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	5190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1726	0	0
T172	0	1730	0	0
T191	103462	0	0	0
T296	0	1734	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	464285476	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	464285476	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	5190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1726	0	0
T172	0	1730	0	0
T191	103462	0	0	0
T296	0	1734	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	5190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1726	0	0
T172	0	1730	0	0
T191	103462	0	0	0
T296	0	1734	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	5190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1726	0	0
T172	0	1730	0	0
T191	103462	0	0	0
T296	0	1734	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	5190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1726	0	0
T172	0	1730	0	0
T191	103462	0	0	0
T296	0	1734	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	5190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1726	0	0
T172	0	1730	0	0
T191	103462	0	0	0
T296	0	1734	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	464285476	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	5190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1726	0	0
T172	0	1730	0	0
T191	103462	0	0	0
T296	0	1734	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T171,T172,T296
0	1	Covered	T171,T172,T296
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T171,T172,T296
1	Covered	T171,T172,T296

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T171,T172,T296
1	Covered	T171,T172,T296

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T171,T172,T296
1	1	Covered	T171,T172,T296

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T171,T172,T296
1	0	Covered	T171,T172,T296
1	1	Covered	T171,T172,T296

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T171,T172,T296

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T171,T172,T296
0	Covered	T171,T172,T296

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T171,T172,T296
0	Covered	T171,T172,T296

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	473016638	464285476	0	0
CheckNGreaterZero_A	983	983	0	0
GntImpliesReady_A	473016638	3190	0	0
GntImpliesValid_A	473016638	3190	0	0
GrantKnown_A	473016638	464285476	0	0
IdxKnown_A	473016638	464285476	0	0
IndexIsCorrect_A	473016638	3190	0	0
NoReadyValidNoGrant_A	473016638	0	0	0
Priority_A	473016638	3190	0	0
ReadyAndValidImplyGrant_A	473016638	3190	0	0
ReqAndReadyImplyGrant_A	473016638	3190	0	0
ReqImpliesValid_A	473016638	3190	0	0
ValidKnown_A	473016638	464285476	0	0
gen_data_port_assertion.DataFlow_A	473016638	3190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	464285476	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T51	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	3190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1064	0	0
T172	0	1063	0	0
T191	103462	0	0	0
T296	0	1063	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	3190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1064	0	0
T172	0	1063	0	0
T191	103462	0	0	0
T296	0	1063	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	464285476	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	464285476	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	3190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1064	0	0
T172	0	1063	0	0
T191	103462	0	0	0
T296	0	1063	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	3190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1064	0	0
T172	0	1063	0	0
T191	103462	0	0	0
T296	0	1063	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	3190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1064	0	0
T172	0	1063	0	0
T191	103462	0	0	0
T296	0	1063	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	3190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1064	0	0
T172	0	1063	0	0
T191	103462	0	0	0
T296	0	1063	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	3190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1064	0	0
T172	0	1063	0	0
T191	103462	0	0	0
T296	0	1063	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	464285476	0	0
T4	75388	75330	0	0
T5	199084	198919	0	0
T6	229194	229074	0	0
T18	224183	224067	0	0
T51	130538	130532	0	0
T85	380511	380401	0	0
T86	88453	88402	0	0
T87	378852	378797	0	0
T88	154449	154394	0	0
T89	348656	348594	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473016638	3190	0	0
T82	512014	0	0	0
T144	351672	0	0	0
T166	50130	0	0	0
T171	76908	1064	0	0
T172	0	1063	0	0
T191	103462	0	0	0
T296	0	1063	0	0
T405	148258	0	0	0
T406	275889	0	0	0
T407	89761	0	0	0
T408	154706	0	0	0
T409	62112	0	0	0