CHIP Simulation Results

Friday June 21 2024 23:02:45 UTC

GitHub Revision: `de38ce313c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40294666978553523170681160506532247841705182588034413483474981853853670477454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.162m	2.923ms	3	3	100.00
		chip_sw_example_rom	2.455m	2.814ms	3	3	100.00
		chip_sw_example_manufacturer	4.262m	2.881ms	3	3	100.00
		chip_sw_example_concurrency	5.913m	2.671ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.400m	6.839ms	5	5	100.00
V1	csr_rw	chip_csr_rw	16.228m	6.700ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.663h	58.680ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	1.896h	38.104ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.038m	3.045ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.896h	38.104ms	4	5	80.00
		chip_csr_rw	16.228m	6.700ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.480s	229.774us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	9.551m	3.747ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	9.551m	3.747ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	9.551m	3.747ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	12.191m	4.937ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	12.191m	4.937ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	12.832m	4.566ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	12.428m	4.361ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	13.806m	4.465ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	50.582m	13.011ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	34.937m	8.491ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	33.659m	13.438ms	5	5	100.00
V1		TOTAL			199	220	90.45
V2	chip_pin_mux	chip_padctrl_attributes	5.121m	5.420ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.121m	5.420ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.700m	2.939ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.278m	3.009ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.395m	4.388ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	29.842m	14.452ms	5	5	100.00
		chip_tap_straps_testunlock0	12.079m	6.283ms	5	5	100.00
		chip_tap_straps_rma	7.702m	4.946ms	4	5	80.00
		chip_tap_straps_prod	25.252m	16.868ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.494m	2.640ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.650m	9.229ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.726m	4.659ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.726m	4.659ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.259m	6.951ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.573m	4.472ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.759m	5.750ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.168h	19.021ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.367m	2.955ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	22.781m	6.375ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.026m	2.783ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.380m	12.170ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.085m	2.750ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.414m	4.892ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.506m	2.641ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	4.819m	3.592ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	13.085m	5.247ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.597m	5.120ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.321m	2.355ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.597m	5.120ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.728m	2.646ms	3	3	100.00
		chip_sw_aes_smoketest	4.317m	3.327ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.142m	3.249ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.700m	2.599ms	3	3	100.00
		chip_sw_csrng_smoketest	4.397m	3.045ms	3	3	100.00
		chip_sw_entropy_src_smoketest	7.438m	2.870ms	3	3	100.00
		chip_sw_gpio_smoketest	5.029m	3.675ms	3	3	100.00
		chip_sw_hmac_smoketest	7.968m	3.794ms	3	3	100.00
		chip_sw_kmac_smoketest	5.003m	2.524ms	3	3	100.00
		chip_sw_otbn_smoketest	19.312m	5.685ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.271m	6.046ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.013m	6.733ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.659m	2.711ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.337m	2.572ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.800m	3.489ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.659m	3.174ms	3	3	100.00
		chip_sw_uart_smoketest	5.471m	3.296ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	4.829m	3.555ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.032m	5.352ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.941h	79.162ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.059h	15.132ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	5.203h	204.426ms	0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	13.485m	3.875ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.772m	11.148ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.205h	60.333ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.695h	65.505ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.952m	5.373ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.952m	5.373ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.896h	38.104ms	4	5	80.00
		chip_same_csr_outstanding	1.418h	32.190ms	20	20	100.00
		chip_csr_hw_reset	6.400m	6.839ms	5	5	100.00
		chip_csr_rw	16.228m	6.700ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.896h	38.104ms	4	5	80.00
		chip_same_csr_outstanding	1.418h	32.190ms	20	20	100.00
		chip_csr_hw_reset	6.400m	6.839ms	5	5	100.00
		chip_csr_rw	16.228m	6.700ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.666m	2.398ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.400s	48.968us	100	100	100.00
		xbar_smoke_large_delays	1.962m	10.215ms	100	100	100.00
		xbar_smoke_slow_rsp	2.101m	7.810ms	100	100	100.00
		xbar_random_zero_delays	56.850s	603.930us	100	100	100.00
		xbar_random_large_delays	19.394m	110.299ms	100	100	100.00
		xbar_random_slow_rsp	20.463m	70.957ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.034m	1.507ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.120s	1.402ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.543m	2.357ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.120s	1.402ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.486m	3.145ms	100	100	100.00
		xbar_access_same_device_slow_rsp	49.838m	170.450ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.358m	2.643ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	10.904m	16.233ms	100	100	100.00
		xbar_stress_all_with_error	11.150m	17.836ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	19.173m	21.099ms	100	100	100.00
		xbar_stress_all_with_reset_error	13.066m	15.987ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.059h	15.132ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.006m	6.785ms	0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	14.101m	5.263ms	0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	52.616m	11.585ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.043h	15.771ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.215h	15.549ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.087h	15.446ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.001h	14.558ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	51.972m	11.407ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	1.164h	15.322ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	59.462m	15.825ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	1.219h	16.040ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	1.020h	14.759ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.460h	18.884ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.488h	24.833ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.711h	24.317ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.687h	24.904ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.483h	23.628ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	6.019m	3.356ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.532m	5.766ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.818m	5.566ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.460m	5.161ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.348m	4.547ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	7.135m	3.946ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.578m	4.968ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.717m	5.451ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.383m	5.428ms	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.415m	4.356ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	7.709m	3.775ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.039m	6.123ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.323m	5.266ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.074m	4.955ms	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	10.581m	5.146ms	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	58.747m	11.504ms	3	3	100.00
		rom_e2e_asm_init_dev	1.226h	16.218ms	3	3	100.00
		rom_e2e_asm_init_prod	1.195h	16.481ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.313h	16.055ms	3	3	100.00
		rom_e2e_asm_init_rma	1.099h	15.241ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.260h	15.163ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.271h	14.930ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.114h	15.256ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.339h	17.304ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.417m	2.907ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.367m	2.955ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.674m	2.570ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.204m	2.364ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	30.088m	9.566ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.263m	19.777ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.263m	19.777ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.426m	4.175ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.271m	6.046ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.426m	4.175ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.348m	8.980ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	17.348m	8.980ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.036m	8.006ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.938m	4.616ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.187m	5.615ms	3	3	100.00
		chip_sw_aes_idle	4.204m	2.364ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.449m	3.111ms	3	3	100.00
		chip_sw_kmac_idle	5.062m	2.666ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.604m	4.807ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	11.455m	4.852ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.997m	5.289ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	10.097m	4.438ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	27.335m	12.960ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.821m	4.377ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.066m	4.045ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.529m	4.018ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.849m	4.389ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.393m	4.335ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.802m	4.699ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.259m	6.951ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	16.826m	11.027ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.529m	4.018ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.849m	4.389ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	11.573m	4.472ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.759m	5.750ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.168h	19.021ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.367m	2.955ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	22.781m	6.375ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.026m	2.783ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.380m	12.170ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.085m	2.750ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.414m	4.892ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.506m	2.641ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.757m	2.643ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	13.883m	4.854ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	20.528m	7.248ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.380h	24.605ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.745m	3.091ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.819m	3.512ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	30.735m	12.207ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.852m	3.347ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.838m	4.654ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	39.384m	18.654ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.050h	21.214ms	1	3	33.33
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.259m	6.951ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.030m	4.604ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.457m	3.637ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.089m	5.760ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	41.056m	9.239ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	35.078m	8.062ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.775m	5.232ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	14.013m	6.990ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.359m	2.761ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.732m	6.380ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	30.739m	24.142ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	7.034m	3.794ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	7.988m	2.900ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.281m	5.381ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	30.739m	24.142ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	30.739m	24.142ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	54.039m	21.023ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	54.039m	21.023ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.137m	5.486ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.263m	19.777ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.980h	37.133ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	6.196m	3.700ms	3	3	100.00
		chip_sw_edn_entropy_reqs	23.392m	5.788ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	6.196m	3.700ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	35.078m	8.062ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	5.419m	3.386ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	37.266m	21.050ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	20.808m	5.434ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	20.759m	5.750ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	13.621m	4.339ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	11.573m	4.472ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.509h	42.894ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	37.266m	21.050ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.354m	3.974ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	36.870m	9.107ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.047m	5.754ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.509h	42.894ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	10.047m	5.754ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.047m	5.754ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	10.047m	5.754ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	10.047m	5.754ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.089m	5.760ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.044m	4.987ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	21.878m	5.661ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	14.498m	5.961ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	14.498m	5.961ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.982m	3.126ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.026m	2.783ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.449m	3.111ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	7.609m	3.315ms	3	3	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	29.080m	6.518ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	14.390m	5.162ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	16.756m	5.672ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.006m	4.704ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.587m	3.972ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	36.870m	9.107ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	38.380m	12.170ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	42.981m	12.664ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	30.088m	9.566ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.045h	13.114ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.145m	2.915ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.225m	3.387ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.085m	2.750ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	36.870m	9.107ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	18.562m	11.619ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.752m	3.150ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.630m	3.067ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.062m	2.666ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.430m	4.858ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	29.842m	14.452ms	5	5	100.00
		chip_tap_straps_rma	7.702m	4.946ms	4	5	80.00
		chip_tap_straps_prod	25.252m	16.868ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.723m	2.914ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	18.562m	11.619ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	18.562m	11.619ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	18.562m	11.619ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	39.880m	9.303ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	10.047m	5.754ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.509h	42.894ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.170m	4.175ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.302m	8.030ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	27.827m	8.895ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.836m	9.084ms	3	3	100.00
		chip_sw_lc_ctrl_transition	18.562m	11.619ms	15	15	100.00
		chip_sw_keymgr_key_derivation	36.870m	9.107ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.887m	8.309ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	18.866m	8.297ms	3	3	100.00
		chip_prim_tl_access	3.044m	4.987ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	16.826m	11.027ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.821m	4.377ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.066m	4.045ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.529m	4.018ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.849m	4.389ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.393m	4.335ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.802m	4.699ms	3	3	100.00
		chip_tap_straps_dev	29.842m	14.452ms	5	5	100.00
		chip_tap_straps_rma	7.702m	4.946ms	4	5	80.00
		chip_tap_straps_prod	25.252m	16.868ms	5	5	100.00
		chip_rv_dm_lc_disabled	10.594m	14.087ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.565m	2.821ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.900m	3.772ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.544m	2.727ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.409m	3.359ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	40.545m	23.551ms	3	3	100.00
		chip_rv_dm_lc_disabled	10.594m	14.087ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.640h	48.560ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.522h	46.679ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	18.899m	11.540ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.586h	48.009ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	40.545m	23.551ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.071m	2.702ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.898m	2.906ms	3	3	100.00
		rom_volatile_raw_unlock	2.042m	2.666ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	18.562m	11.619ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	37.266m	21.050ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.611m	3.210ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.870m	9.107ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.364m	4.309ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.186m	2.935ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	37.266m	21.050ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.611m	3.210ms	3	3	100.00
		chip_sw_keymgr_key_derivation	36.870m	9.107ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.364m	4.309ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.186m	2.935ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	18.562m	11.619ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.256m	15.176ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.723m	2.914ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.170m	4.175ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.302m	8.030ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	27.827m	8.895ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	22.836m	9.084ms	3	3	100.00
		chip_sw_lc_ctrl_transition	18.562m	11.619ms	15	15	100.00
		chip_prim_tl_access	3.044m	4.987ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.044m	4.987ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.625h	27.178ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.505m	7.199ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	34.897m	23.584ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.945m	7.305ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.572m	7.555ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.476m	7.146ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	26.520m	24.713ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	28.123m	15.678ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	17.348m	8.980ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	23.210m	11.631ms	2	3	66.67
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.094m	5.589ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.505m	7.199ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.253m	5.169ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.102h	44.958ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.723m	6.411ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.619m	6.203ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.153m	20.463ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	18.732m	6.380ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	23.055m	9.573ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	51.511m	23.409ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.395m	2.957ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.089m	5.760ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.887m	8.309ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.887m	8.309ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	23.055m	9.573ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	44.153m	20.463ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	11.094m	5.589ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.271m	6.046ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.604m	3.327ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.442m	6.154ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.892m	4.898ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	35.092m	14.446ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.366m	2.772ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.089m	5.760ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	33.339m	7.603ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	25.831m	6.257ms	3	3	100.00
		chip_plic_all_irqs_10	11.323m	4.357ms	3	3	100.00
		chip_plic_all_irqs_20	15.709m	5.385ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.430m	3.265ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.391m	3.302ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.059h	15.132ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.098m	7.384ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.443m	4.721ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.625m	3.051ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.835m	2.607ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.364m	4.309ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.414m	4.892ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	13.945m	8.038ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.728m	6.932ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	18.866m	8.297ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.089m	5.760ms	98	100	98.00
		chip_sw_data_integrity_escalation	14.726m	4.659ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.863m	2.600ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.847m	2.915ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	6.783m	3.605ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.261m	4.026ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	38.240m	8.735ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.299h	32.160ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	55.473m	11.665ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	7.119m	2.708ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.430m	4.858ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.089m	5.760ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.497m	2.924ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	35.092m	14.446ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.829m	4.933ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.573m	4.703ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	25.276m	11.393ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	41.056m	9.239ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	33.339m	7.603ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	26.993m	7.673ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.572h	255.478ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	40.845m	20.957ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	26.499m	13.695ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.604m	3.327ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	8.663m	4.570ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.003m	3.886ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	7.702m	4.946ms	4	5	80.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.594m	14.087ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2603	2644	98.45
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	7.108m	3.234ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	24.289m	8.488ms	0	1	0.00
		rom_e2e_jtag_debug_dev	30.603m	9.975ms	0	1	0.00
		rom_e2e_jtag_debug_rma	24.635m	8.912ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	56.890m	42.206ms	1	1	100.00
		rom_e2e_jtag_inject_dev	1.056h	27.572ms	1	1	100.00
		rom_e2e_jtag_inject_rma	1.041h	37.487ms	1	1	100.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash			0	0	--
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.428m	3.444ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	11.664m	3.135ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	25.742m	5.869ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	36.836m	10.797ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.929m	3.268ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.448m	6.127ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	//sw/device/tests:i2c_host_override_test			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.785m	2.508ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.371m	4.861ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	10.074m	5.726ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.031m	5.437ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	23.055m	9.573ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.089m	5.760ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	//sw/device/tests:spi_passthru_test			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	12.191m	4.937ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.018h	18.621ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	24.289m	8.488ms	0	1	0.00
		rom_e2e_jtag_debug_dev	30.603m	9.975ms	0	1	0.00
		rom_e2e_jtag_debug_rma	24.635m	8.912ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.834m	4.861ms	3	3	100.00
V3		TOTAL			35	45	77.78
	Unmapped tests	chip_sival_flash_info_access	6.072m	3.628ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	15.425m	5.568ms	3	3	100.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	4.684m	3.010ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.065h	17.503ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	22.434m	5.665ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.671m	5.092ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	9.532m	4.028ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.197m	5.748ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	6.330m	2.994ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	4.806m	2.561ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear	6.372m	3.163ms	3	3	100.00
		TOTAL			2873	2945	97.56

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	11	11	11	100.00
V1	18	18	16	88.89
V2	285	270	243	85.26
V2S	1	1	1	100.00
V3	90	21	15	16.67

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.49	93.94	95.40	--	94.74	97.53	99.51

Failure Buckets

UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.30458351516518299032425558028209444666358934853288661634106699239841633616186
    Line 371, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2676.117177 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2676.117177 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.62212425788905063600253601941756364449082960571497314418542639759510038263683
    Line 397, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2390.853388 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2390.853388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.78573544856150193292463316262354218422663843243086636551131505684954474472419
    Line 1140, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 3356.418311 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:02108421
  "
  UVM_INFO @ 3356.418311 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.41173845551095200701708181787960822104645349462223054585921859608146840943291
    Line 1074, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_ERROR @ 5765.651617 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:21084210
  "
  UVM_INFO @ 5765.651617 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod.104390753171714223119341171211138988604071974405792633092406978625810775081662
    Line 1027, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
```
  UVM_ERROR @ 5566.203759 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:2318c631
  "
  UVM_INFO @ 5566.203759 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.28197835244454125184739701977884428139664870241978004458569156340720161625514
    Line 1127, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
```
  UVM_ERROR @ 5160.573179 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:25294a52
  "
  UVM_INFO @ 5160.573179 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_rma.90129591631194502880549287622755771834323321344079624263422316249842634160040
    Line 1147, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
```
  UVM_ERROR @ 4546.691235 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:07535603
  LCV:2739ce73
  "
  UVM_INFO @ 4546.691235 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
- ... and 10 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.67714619935639995388695666950230583898082955405122565461376605060534688031881
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:ec6c2506-1a28-4c22-b24a-a52c6e3c9a03
```
  - 1.chip_sw_rv_timer_systick_test.15591029820792485816905625227015318880702560194273019908241104484782167981709
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:b6ee535a-aeb4-4f4a-8abc-132d2c9f45ca
```
  - ... and 1 more failures.
- Test chip_sw_coremark has 1 failures.
  - 0.chip_sw_coremark.59649509127758331779693591054885648238814818507353630629680971087438626311406
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
```
  Job ID: smart:3090b941-a8d1-4d89-8fbe-308ca4097b0a
```
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.93617454402862502108460204886461399498723856542957933743791709056308266701173
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:4dcf0ce7-6b34-4d02-89a5-938ab2283261
```
  - 1.chip_sw_ast_clk_rst_inputs.25893420079818259521359647153635800353792585580998560124398351212676736393217
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:c13dfc43-8c83-485f-b57f-f0c20f025c0d
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.45459584029801289080484761322572047330900160759363539719518433855536141337625
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:deccf04e-2c0d-4eeb-8b25-907f222cbae4
```
  - 1.chip_sw_power_virus.32185181546063700922673267806925420243647793318678866532875700360931161948876
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:a9df7e37-eec8-44ac-b090-4749980b3292
```
  - ... and 1 more failures.
- Test chip_sw_csrng_edn_concurrency_reduced_freq has 2 failures.
  - 1.chip_sw_csrng_edn_concurrency_reduced_freq.90938174034861096263608800284752853115457262609585540429910909214938079419666
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:cefc562a-8369-4669-a7be-0ebbfe58e183
```
  - 2.chip_sw_csrng_edn_concurrency_reduced_freq.36248199113797972599333660760845524596057595851858438181204366883269729948036
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
```
  Job ID: smart:f6c1026e-7b9e-416a-8725-4d7f61f35344
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.15313581583690391419509192968150975945288935699322304379994067058934591345007
    Line 917, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15017.490438 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15017.490438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.4721093461331532786450625017676993381078178860527547693306087108965536011465
    Line 826, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15176.006912 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15176.006912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 3 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.70113611010569834359691106765341302402829275964958038390379358795550587091477
    Line 826, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3863.365695 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3863.365695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_rv_dm_access_after_wakeup.88036108110168949501756980006801481793926381081618549392026587071859235676389
    Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 3886.300151 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
  UVM_INFO @ 3886.300151 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_exception_c has 3 failures.
  - 0.rom_e2e_shutdown_exception_c.112216432278585808349177418367255120070172931845615273546779557467857062481271
    Line 1015, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 5177.403177 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 5177.403177 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_exception_c.52121294027776523634570849461573008577857344009586049040485952662297024601549
    Line 1108, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_ERROR @ 5102.815969 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:01495202
  LCV:2739ce73
  "
  UVM_INFO @ 5102.815969 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
- Test rom_e2e_shutdown_output has 3 failures.
  - 0.rom_e2e_shutdown_output.86322467462336029824142241454620266607108502694746784571051256319196326770214
    Line 1048, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 6863.755111 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 6863.755111 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - 1.rom_e2e_shutdown_output.13061096046476290321037146759765754139151054854005531860132542996315572737208
    Line 1115, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
  UVM_ERROR @ 6785.217221 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
  GIT:" == "BFV:0142500d
  LCV:02108421
  "
  UVM_INFO @ 6785.217221 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.109470754428480432555669213536732159359774393990133539784767636542259792206701
    Line 817, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 8487.780904 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 8487.780904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.50647437831832445025331076400216459873303553000561260038075693609236051036664
    Line 862, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 9975.429552 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 9975.429552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.56690011101605985201197771533601064998239031417746991901460013106785878630425
    Line 826, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 8912.336974 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
  UVM_INFO @ 8912.336974 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 3 failures:

Test rom_raw_unlock has 3 failures.

0.rom_raw_unlock.46930283783567952358012576375617296237141265231098376760061432992656885567547
Line 882, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 204426.347484 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 204426.347484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_raw_unlock.30846321762741073521365053356858470566331175912951327807081725839199162340018
Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log

  UVM_ERROR @ 205603.663223 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
  
  UVM_INFO @ 205603.663223 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
- Test chip_sw_all_escalation_resets has 2 failures.
  - 13.chip_sw_all_escalation_resets.48762072884699907056338683836953698647002671713439691880521499659002028719845
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3421.921240 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3421.921240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.chip_sw_all_escalation_resets.100555197905799366099189273632963954928222802603876421522991253861852179020418
    Line 869, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/46.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2429.658530 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2429.658530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.89955840895066070887230257801308319415528047483951750280374030069945374223623
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:3f39b3bd-79fd-4e97-afa8-c04154f50569
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.
  - 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.65812095826976157602951493454162528395113115386699508682117905525961837238492
    Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 6945.523152 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 6945.523152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits * and * set in filter status, got status * has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 1 failures.
  - 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.31100880109087868120808425379929239469676488142511014495245951790942629436307
    Line 818, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6104.265656 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:250)] CHECK-fail: Expected bits 5 and 8 set in filter status, got status 0x100
  UVM_INFO @ 6104.265656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test chip_tap_straps_rma has 1 failures.
  - 2.chip_tap_straps_rma.47116469928364342034802303328157428146756053086505942054269106699948032318263
    Line 5974, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest/run.log
```
  UVM_ERROR @ 4103.794981 us: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @ 4103.794981 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 13.chip_sw_alert_handler_lpg_sleep_mode_alerts.73795077108745958460062850969081865058965032100050103259341773651003511065581
    Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4632.583592 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
  UVM_INFO @ 4632.583592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```