302b24f3c6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 3.630m | 3.343ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.330m | 2.312ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.243m | 2.488ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.610m | 2.634ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 7.296m | 8.009ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 11.651m | 5.325ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 21.656m | 11.460ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.924h | 56.814ms | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 2.028m | 2.647ms | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.924h | 56.814ms | 4 | 5 | 80.00 |
| chip_csr_rw | 11.651m | 5.325ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 11.090s | 263.151us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 9.158m | 3.425ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 9.158m | 3.425ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 9.158m | 3.425ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 13.909m | 4.948ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 13.909m | 4.948ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 10.801m | 4.305ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 13.345m | 5.164ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 13.826m | 4.601ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 56.853m | 12.956ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 45.226m | 13.655ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 34.528m | 14.047ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 199 | 220 | 90.45 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.970m | 5.098ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.970m | 5.098ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 7.415m | 3.532ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 9.237m | 7.370ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.910m | 4.070ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 30.761m | 16.259ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 15.717m | 9.278ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_rma | 9.863m | 6.110ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.011m | 15.392ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.741m | 2.948ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 24.960m | 8.694ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 15.286m | 6.527ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 15.286m | 6.527ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 21.431m | 8.492ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 43.327m | 19.192ms | 1 | 3 | 33.33 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 11.657m | 4.071ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.149m | 5.854ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.117h | 19.326ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.772m | 2.915ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 21.634m | 7.162ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.538m | 2.379ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 34.799m | 10.727ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.053m | 3.402ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.262m | 4.347ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.804m | 3.464ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 6.542m | 2.875ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 18.984m | 8.520ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.340m | 5.371ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.612m | 2.332ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 8.340m | 5.371ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 5.185m | 2.873ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.764m | 2.736ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.160m | 3.400ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.486m | 2.966ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.353m | 2.492ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.623m | 3.222ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.173m | 2.887ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.845m | 3.429ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.927m | 3.014ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 33.128m | 9.309ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.510m | 6.203ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 9.431m | 5.754ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 5.600m | 2.371ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.529m | 2.840ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.373m | 3.137ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.455m | 2.948ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.808m | 3.425ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 4.732m | 2.769ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 11.123m | 4.569ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 0 | 3 | 0.00 | ||
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 59.223m | 14.390ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 3.931h | 205.420ms | 0 | 3 | 0.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 12.317m | 4.817ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 8.362m | 4.891ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.059h | 59.078ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.614h | 64.341ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 9.460m | 5.364ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 9.460m | 5.364ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.924h | 56.814ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.346h | 31.537ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.296m | 8.009ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.651m | 5.325ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.924h | 56.814ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.346h | 31.537ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.296m | 8.009ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.651m | 5.325ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.650m | 2.426ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.160s | 45.710us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.019m | 10.446ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.120m | 7.061ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 55.910s | 637.417us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 22.784m | 110.274ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 23.256m | 69.865ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.012m | 1.433ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.082m | 1.336ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.655m | 2.553ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.082m | 1.336ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 3.156m | 4.597ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 55.801m | 175.263ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.462m | 2.701ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 13.469m | 18.935ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 12.011m | 17.384ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 18.574m | 8.270ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 14.244m | 8.722ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 59.223m | 14.390ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 53.881m | 19.872ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.124h | 14.202ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 47.149m | 11.535ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.245h | 14.217ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 57.134m | 14.662ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.044h | 14.444ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.050h | 14.079ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 1.048h | 10.663ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.019h | 14.516ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 58.825m | 14.675ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 55.563m | 14.016ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 56.451m | 14.257ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.610h | 18.084ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.529h | 22.520ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.762h | 22.844ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.530h | 22.878ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.652h | 22.852ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.082h | 17.504ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.555h | 22.399ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.438h | 22.304ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.604h | 21.671ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.828h | 22.128ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 44.674m | 11.270ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 51.349m | 14.457ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 59.307m | 13.650ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.013h | 14.058ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 51.958m | 13.987ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 44.713m | 10.421ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 57.322m | 13.718ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.173h | 14.331ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 56.781m | 13.508ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 1.051h | 14.093ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 1.061h | 10.893ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.089h | 14.844ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.286h | 14.225ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 59.449m | 14.653ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 59.489m | 13.858ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.102h | 15.540ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 59.951m | 14.730ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.044h | 15.197ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.119h | 15.986ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 6.064m | 3.147ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.772m | 2.915ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.472m | 3.669ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.026m | 3.313ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 31.181m | 9.750ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.273m | 19.888ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.273m | 19.888ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.840m | 3.984ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 9.510m | 6.203ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.840m | 3.984ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 13.562m | 9.938ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 13.562m | 9.938ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.548m | 7.304ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 11.938m | 5.907ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 19.279m | 6.536ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.026m | 3.313ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.902m | 2.853ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.587m | 3.389ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 10.475m | 4.767ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 12.166m | 5.332ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.372m | 3.994ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 9.932m | 5.286ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 25.686m | 9.385ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.177m | 4.275ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 13.318m | 4.825ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.875m | 4.373ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.951m | 4.694ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.264m | 4.302ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 14.445m | 4.770ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 21.431m | 8.492ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 21.030m | 14.243ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.875m | 4.373ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.951m | 4.694ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 11.657m | 4.071ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.149m | 5.854ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.117h | 19.326ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.772m | 2.915ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 21.634m | 7.162ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.538m | 2.379ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 34.799m | 10.727ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.053m | 3.402ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.262m | 4.347ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.804m | 3.464ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.661m | 3.289ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 12.855m | 5.635ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 19.663m | 7.632ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.211h | 24.163ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.723m | 2.827ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.704m | 3.226ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 28.759m | 10.820ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.134m | 3.363ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 11.001m | 6.003ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 38.503m | 26.343ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 21.431m | 8.492ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.780m | 4.430ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.571m | 3.699ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 15.326m | 5.669ms | 97 | 100 | 97.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 32.732m | 7.882ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 30.175m | 8.317ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 9.820m | 4.628ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 13.111m | 6.403ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.240m | 3.453ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 21.245m | 8.186ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 31.002m | 23.973ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.195m | 3.275ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 40.710s | 10.400us | 0 | 3 | 0.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.986m | 4.943ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 31.002m | 23.973ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 31.002m | 23.973ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.015h | 19.962ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.015h | 19.962ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.414m | 6.200ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.273m | 19.888ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.779h | 26.444ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 5.035m | 3.181ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 23.467m | 8.321ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.035m | 3.181ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 30.175m | 8.317ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 5.016m | 3.342ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 42.261m | 18.209ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 18.683m | 5.608ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.149m | 5.854ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 12.032m | 4.590ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 11.657m | 4.071ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.500h | 43.469ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 42.261m | 18.209ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.681m | 3.305ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 46.748m | 13.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 12.412m | 4.965ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.500h | 43.469ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 12.412m | 4.965ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 12.412m | 4.965ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 12.412m | 4.965ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 12.412m | 4.965ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 15.326m | 5.669ms | 97 | 100 | 97.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 7.474m | 9.336ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 22.046m | 6.244ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.308m | 5.076ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 11.308m | 5.076ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.077m | 3.091ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.538m | 2.379ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.902m | 2.853ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.065m | 3.201ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 24.547m | 6.213ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 14.767m | 4.761ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 17.309m | 6.539ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 13.824m | 5.393ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 9.608m | 4.356ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 46.748m | 13.000ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 34.799m | 10.727ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 31.599m | 8.576ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 31.181m | 9.750ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.461h | 16.047ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.303m | 2.794ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.039m | 3.061ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.053m | 3.402ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 46.748m | 13.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.496m | 10.957ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.060m | 2.990ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.656m | 3.452ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.587m | 3.389ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.705m | 4.791ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 30.761m | 16.259ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 9.863m | 6.110ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.011m | 15.392ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.697m | 2.549ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.496m | 10.957ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.496m | 10.957ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.496m | 10.957ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 40.107m | 10.398ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 12.412m | 4.965ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.500h | 43.469ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.807m | 4.925ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 26.050m | 9.206ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.572m | 8.652ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 27.259m | 8.903ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.496m | 10.957ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 46.748m | 13.000ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 12.165m | 9.125ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 20.277m | 7.339ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 7.474m | 9.336ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 21.030m | 14.243ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.177m | 4.275ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 13.318m | 4.825ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.875m | 4.373ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.951m | 4.694ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.264m | 4.302ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 14.445m | 4.770ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 30.761m | 16.259ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 9.863m | 6.110ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 28.011m | 15.392ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 10.602m | 14.940ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 5.053m | 2.989ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 1.951m | 2.828ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.734m | 2.738ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.720m | 3.667ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 40.870m | 29.696ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 10.602m | 14.940ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.496h | 49.665ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.734h | 50.021ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 22.637m | 11.819ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.520h | 47.823ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 40.870m | 29.696ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.213m | 2.234ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 1.937m | 2.595ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.026m | 2.911ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.496m | 10.957ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 42.261m | 18.209ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.735m | 3.279ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 46.748m | 13.000ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 9.855m | 4.262ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.938m | 3.351ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 42.261m | 18.209ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.735m | 3.279ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 46.748m | 13.000ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 9.855m | 4.262ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.938m | 3.351ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.496m | 10.957ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 18.784m | 14.704ms | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.697m | 2.549ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.807m | 4.925ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 26.050m | 9.206ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.572m | 8.652ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 27.259m | 8.903ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.496m | 10.957ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 7.474m | 9.336ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 7.474m | 9.336ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.546h | 26.620ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 8.229m | 6.866ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 33.804m | 24.967ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.303m | 7.338ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 13.075m | 9.762ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 9.594m | 7.298ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 29.607m | 21.809ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 27.148m | 16.414ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 13.562m | 9.938ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 26.183m | 11.846ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 12.502m | 5.164ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 8.229m | 6.866ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 10.184m | 4.020ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1.066h | 32.508ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 11.814m | 7.297ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 8.763m | 5.465ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 42.360m | 29.350ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 21.245m | 8.186ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 29.293m | 10.040ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 36.139m | 32.433ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.326m | 3.370ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 15.326m | 5.669ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 12.165m | 9.125ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 12.165m | 9.125ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 29.293m | 10.040ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 42.360m | 29.350ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 12.502m | 5.164ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.510m | 6.203ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 10.757m | 5.056ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 13.401m | 4.836ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 10.087m | 3.851ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 34.692m | 11.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.894m | 3.092ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 15.326m | 5.669ms | 97 | 100 | 97.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 30.199m | 8.198ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 21.828m | 6.113ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 10.222m | 4.931ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 16.754m | 4.428ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.303m | 3.282ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.212m | 3.315ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 59.223m | 14.390ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 14.385m | 7.002ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.757m | 4.541ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.282m | 4.093ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 6.178m | 2.913ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 9.855m | 4.262ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 12.262m | 4.347ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 11.381m | 7.698ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 12.482m | 7.139ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 20.277m | 7.339ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 15.326m | 5.669ms | 97 | 100 | 97.00 |
| chip_sw_data_integrity_escalation | 15.286m | 6.527ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 4.238m | 3.468ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 3.462m | 2.741ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 7.294m | 4.000ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 11.499m | 4.409ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 38.395m | 7.766ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 1.881h | 31.404ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 49.095m | 11.937ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.612m | 3.722ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.705m | 4.791ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 15.326m | 5.669ms | 97 | 100 | 97.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.748m | 3.619ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 34.692m | 11.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 5.154m | 3.754ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.399m | 4.317ms | 86 | 90 | 95.56 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 23.641m | 11.230ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 32.732m | 7.882ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 30.199m | 8.198ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 30.659m | 8.036ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.642h | 255.611ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 47.275m | 20.598ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 28.798m | 13.965ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 10.757m | 5.056ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 7.682m | 4.357ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 11.533m | 4.085ms | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 9.863m | 6.110ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 10.602m | 14.940ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2616 | 2644 | 98.94 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.749m | 3.169ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.793h | 71.364ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 15.959m | 5.804ms | 0 | 3 | 0.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 43.658m | 12.502ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 41.596m | 13.705ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 45.573m | 12.776ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 52.848m | 41.623ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_inject_dev | 48.494m | 41.760ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_inject_rma | 1.002h | 48.117ms | 0 | 1 | 0.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | ||
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 7.897m | 3.756ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 9.903m | 2.768ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 36.248m | 7.015ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 34.114m | 8.627ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.858m | 2.815ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 23.360m | 5.267ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | //sw/device/tests:i2c_host_override_test | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.603m | 2.603ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 12.874m | 5.628ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 10.589m | 5.720ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 9.934m | 4.924ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 29.293m | 10.040ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 15.326m | 5.669ms | 97 | 100 | 97.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 13.909m | 4.948ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.210h | 19.982ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 43.658m | 12.502ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 41.596m | 13.705ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 45.573m | 12.776ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.602m | 5.708ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 36 | 45 | 80.00 | |||
| Unmapped tests | chip_sival_flash_info_access | 6.293m | 3.772ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 14.083m | 5.493ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 6.005m | 3.188ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.104h | 17.118ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 18.888m | 5.209ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 16.646m | 4.083ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 9.373m | 4.068ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 9.829m | 6.709ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 7.383m | 3.617ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.931m | 2.474ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 6.263m | 2.904ms | 3 | 3 | 100.00 | ||
| TOTAL | 2887 | 2945 | 98.03 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 11 | 100.00 |
| V1 | 18 | 18 | 16 | 88.89 |
| V2 | 285 | 270 | 260 | 91.23 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 21 | 16 | 17.78 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.99 | 95.52 | 94.01 | 95.51 | -- | 94.89 | 96.47 | 99.55 |
UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
0.chip_csr_mem_rw_with_rand_reset.13451426109310029274062526452263271186297114314529586722211186832654614865943
Line 376, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1826.003628 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1826.003628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_mem_rw_with_rand_reset.38121561403873197671975626956134703134510516875156841769055458857479267148219
Line 396, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2473.896348 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2473.896348 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 12 failures:
Test chip_sw_uart_tx_rx_bootstrap has 3 failures.
0.chip_sw_uart_tx_rx_bootstrap.89313260285107094635223820650425145204368306178500105686094324955546045370153
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
Job ID: smart:ada0c398-c957-4af3-8505-3be407e43078
1.chip_sw_uart_tx_rx_bootstrap.36771865388427979390339915332727593680510068117438843148304784560598717162728
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_uart_tx_rx_bootstrap/latest/run.log
Job ID: smart:2dfdde8c-2a7a-406c-97ec-6099b3f88a73
... and 1 more failures.
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.41211794063958791168414235052472261517652153123041165577492655775634576598211
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:96e34535-7a96-473e-8f33-46fe39978147
1.chip_sw_rv_timer_systick_test.250941811910175183738786025049939407695294841714685827278771679275288662303
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:3cf2e08f-dba1-4405-b6b1-3d6966955d61
... and 1 more failures.
Test chip_sw_csrng_edn_concurrency_reduced_freq has 3 failures.
0.chip_sw_csrng_edn_concurrency_reduced_freq.46621807939644976599225717570405425301526250761335915716949930375978581730305
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
Job ID: smart:08e9b066-eb4b-478b-a7d7-ce4721ad9d64
1.chip_sw_csrng_edn_concurrency_reduced_freq.45876182360621259689933495769867419440851543646170961425370627497474414554561
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
Job ID: smart:3620c3bb-d773-4638-8929-bcd7e214847d
... and 1 more failures.
Test chip_sw_ast_clk_rst_inputs has 2 failures.
0.chip_sw_ast_clk_rst_inputs.85838870250178135453483437699991738890250932470143087896596468042167166363108
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:25269b3d-dc4c-47a6-a491-456072b03716
2.chip_sw_ast_clk_rst_inputs.33520356693968803408303378148999705718006395673150967399417752002132202838917
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_ast_clk_rst_inputs/latest/run.log
Job ID: smart:deccff5d-63a7-4717-9de6-83d4a1501ae3
Test rom_raw_unlock has 1 failures.
1.rom_raw_unlock.15173006345507055936442253278792175414406892859228553593494182168849844398326
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log
Job ID: smart:dc38fb62-ada8-425a-b807-fb590efb99c9
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:
8.chip_sw_alert_handler_lpg_sleep_mode_alerts.35954718438000871549793428899743319571308609138070589112072213266951367072919
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4181.015692 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 4181.015692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.chip_sw_alert_handler_lpg_sleep_mode_alerts.46649166813858234450162905461403952582625779919366965681567246706205467191707
Line 849, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3497.588914 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 3497.588914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
0.chip_sw_sysrst_ctrl_outputs.14805675013507142956562500397580259590762280562384680802451058311367046146914
Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
UVM_FATAL @ 10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_sysrst_ctrl_outputs.53950104828441787558748384895746874067451348450448066930200580880134338019571
Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
UVM_FATAL @ 10.340001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
0.chip_sw_lc_ctrl_program_error.49118868193711025261592361760312311529907482818955466483604793788823664749838
Line 906, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14623.056048 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14623.056048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_lc_ctrl_program_error.14959339509836886537550399754274673953326577185766876752123403754090823195814
Line 836, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14704.445768 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14704.445768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
0.chip_sw_rv_dm_access_after_wakeup.61351829745873755356335918440804278232872262790281567641292778477431275505853
Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 4084.528951 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 4084.528951 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_dm_access_after_wakeup.3304045667515375040813432422315236200306675800421584754173084195693206433163
Line 831, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 3594.807346 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 3594.807346 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:178) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 3 failures:
0.chip_sw_power_virus.16899409467895738570525081229442811518401054386989801613105436055800709037563
Line 1034, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
UVM_ERROR @ 5804.198028 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
UVM_INFO @ 5804.198028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_power_virus.53829546941676606630283713711983652002782655939014760238491347074394256137381
Line 991, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
UVM_ERROR @ 5067.859644 us: (chip_sw_power_virus_vseq.sv:178) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
UVM_INFO @ 5067.859644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_inject_test_unlocked0.23019435629660757177411581955556645099721887217816830948357194430905979747326
Line 807, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
UVM_FATAL @ 41622.681872 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 41622.681872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_dev has 1 failures.
0.rom_e2e_jtag_inject_dev.112039055959436145440441817368797955743994523694695343638874280656261156972573
Line 801, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
UVM_FATAL @ 41759.743105 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 41759.743105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_inject_rma has 1 failures.
0.rom_e2e_jtag_inject_rma.14140487506051242291117335797653648446124856794259484334901955196436895199943
Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
UVM_FATAL @ 48116.726223 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 48116.726223 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
31.chip_sw_all_escalation_resets.49823560972686393573018938233986000211964627542840179911745476673799587422918
Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3181.117426 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3181.117426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
60.chip_sw_all_escalation_resets.7895956323121333683276461305331441216864438181082922446579702082935274225181
Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3354.498636 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3354.498636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:
0.rom_raw_unlock.85234236956318403212334013605138880674255733870795483562126791472489688894563
Line 794, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
UVM_ERROR @ 206091.687171 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
UVM_INFO @ 206091.687171 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rom_raw_unlock.81997551964805051316740040779287279493421126753154893248946471847679486501139
Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log
UVM_ERROR @ 205420.209919 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
UVM_INFO @ 205420.209919 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
1.chip_csr_aliasing.36000670351058334837154508632720628750298791402673478989064514176946348299472
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_aliasing/latest/run.log
Job ID: smart:eed17f9c-6b09-4c4c-9c81-2c59aff4941e
UVM_ERROR @ * us: (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
3.chip_tap_straps_testunlock0.81986301512261275931999686295060704340962286119354358253939420647165624706106
Line 5976, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_testunlock0/latest/run.log
UVM_ERROR @ 3556.755544 us: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
UVM_INFO @ 3556.755544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---