Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1493667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31694595

1

T5

9677

T6

23500

T17

13466

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	22422096	1			T5	3584		T6	18320		T17	5559
values[0x0]	9271632	1			T5	6093		T6	5180		T17	7907
values[0x1]	1494534	1			T5	601		T6	6111		T17	941

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9588	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33178674

1

T5

10278

T6

29611

T17

14407

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16579337	1			T5	5140		T6	14806		T17	7204
valid_sources[0x01]	16578349	1			T5	5138		T6	14805		T17	7203
valid_sources[0x02]	2471	1			T20	4		T55	2095		T62	60
valid_sources[0x03]	376	1			T18	1		T20	1		T250	2
valid_sources[0x04]	331	1			T20	1		T250	1		T57	16
valid_sources[0x05]	365	1			T62	69		T109	36		T243	56
valid_sources[0x06]	2082	1			T20	1		T250	1		T57	1727
valid_sources[0x07]	452	1			T20	1		T81	2		T250	2
valid_sources[0x08]	409	1			T18	2		T250	1		T62	54
valid_sources[0x09]	388	1			T108	39		T57	16		T62	61
valid_sources[0x0a]	415	1			T18	1		T250	1		T56	16
valid_sources[0x0b]	411	1			T18	1		T20	2		T62	68
valid_sources[0x0c]	376	1			T20	4		T57	16		T62	73
valid_sources[0x0d]	703	1			T20	1		T81	5		T56	243
valid_sources[0x0e]	560	1			T18	1		T250	1		T55	16
valid_sources[0x0f]	360	1			T18	1		T20	1		T56	36
valid_sources[0x10]	406	1			T18	1		T62	66		T109	55
valid_sources[0x11]	392	1			T20	2		T62	82		T109	49
valid_sources[0x12]	334	1			T18	1		T20	2		T62	45
valid_sources[0x13]	335	1			T18	2		T20	1		T62	41
valid_sources[0x14]	415	1			T18	1		T250	3		T56	16
valid_sources[0x15]	455	1			T18	1		T56	16		T62	36
valid_sources[0x16]	417	1			T18	2		T20	1		T81	2
valid_sources[0x17]	358	1			T18	7		T81	2		T62	63
valid_sources[0x18]	425	1			T18	1		T20	1		T250	3
valid_sources[0x19]	399	1			T62	85		T109	52		T243	68
valid_sources[0x1a]	386	1			T20	1		T62	52		T109	36
valid_sources[0x1b]	432	1			T20	2		T62	45		T109	51
valid_sources[0x1c]	339	1			T62	45		T109	61		T243	62
valid_sources[0x1d]	453	1			T250	1		T56	110		T62	70
valid_sources[0x1e]	434	1			T81	1		T250	1		T57	16
valid_sources[0x1f]	394	1			T81	6		T62	52		T109	61
valid_sources[0x20]	493	1			T18	1		T20	1		T57	149

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22422096

1

T5

3584

T6

18320

T17

5559

values[0x0]

all_enables

biggest_size

9266795

1

T5

6093

T6

5180

T17

7907

values[0x1]

all_enables

biggest_size

5704

1

T18

17

T20

23

T81

23