Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.09			84.09

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	83.91			83.91
tb.dut.top_earlgrey.u_i2c1	84.00			84.00
tb.dut.top_earlgrey.u_i2c2	84.00			84.00

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.91			83.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.91			83.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.00			84.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	352	296	84.09
Total Bits 0->1	176	148	84.09
Total Bits 1->0	176	148	84.09

Ports	54	40	74.07
Port Bits	352	296	84.09
Port Bits 0->1	176	148	84.09
Port Bits 1->0	176	148	84.09

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T120,T193	Yes	T6,T120,T193	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T6,T120,T193	Yes	T6,T120,T193	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T6,T120,T72	Yes	T6,T120,T72	INPUT
tl_o.a_ready	Yes	Yes	T6,T120,T72	Yes	T6,T120,T72	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T193,T89	Yes	T6,T193,T89	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T6,T120,T193	Yes	T6,T120,T72	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T120,*T123,*T194	Yes	T6,T120,T72	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T6,T120,T193	Yes	T6,T120,T72	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T6,*T120,*T193	Yes	T6,T120,T72	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T120,T123,T194	Yes	T6,T120,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T120,*T193	Yes	T6,T120,T193	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T120,T72	Yes	T6,T120,T72	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T123,T195	Yes	T72,T123,T195	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T196,T178,T30	Yes	T178,T30,T179	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T178,T30,T179	Yes	T196,T178,T30	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T123,T195	Yes	T72,T123,T195	OUTPUT
cio_scl_i	Yes	Yes	T6,T193,T197	Yes	T6,T193,T197	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T6,T193,T198	Yes	T6,T193,T198	OUTPUT
cio_sda_i	Yes	Yes	T6,T193,T197	Yes	T6,T193,T197	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T6,T193,T197	Yes	T6,T193,T197	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T6,T193,T89	Yes	T6,T193,T89	OUTPUT
intr_rx_threshold_o	Yes	Yes	T6,T193,T89	Yes	T6,T193,T89	OUTPUT
intr_acq_threshold_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_rx_overflow_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_controller_halt_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_scl_interference_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_sda_interference_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_sda_unstable_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_cmd_complete_o	Yes	Yes	T6,T193,T89	Yes	T6,T193,T89	OUTPUT
intr_tx_stretch_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_tx_threshold_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_acq_stretch_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_unexp_stop_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_host_timeout_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	348	292	83.91
Total Bits 0->1	174	146	83.91
Total Bits 1->0	174	146	83.91

Ports	54	40	74.07
Port Bits	348	292	83.91
Port Bits 0->1	174	146	83.91
Port Bits 1->0	174	146	83.91

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T120,T89,T101	Yes	T120,T89,T101	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T120,T89,T101	Yes	T120,T89,T101	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T120,T72,T123	Yes	T120,T72,T123	INPUT
tl_o.a_ready	Yes	Yes	T120,T72,T123	Yes	T120,T72,T123	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T89,T101,T199	Yes	T89,T101,T199	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T120,T123,T89	Yes	T120,T72,T123	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T120,*T123,*T194	Yes	T120,T72,T123	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T120,T123,T89	Yes	T120,T72,T123	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T120,*T123,*T89	Yes	T120,T72,T123	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T120,T123,T194	Yes	T120,T72,T123	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T120,*T89,*T101	Yes	T120,T89,T101	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T120,T72,T123	Yes	T120,T72,T123	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T123,T196	Yes	T72,T123,T196	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T196,T178,T30	Yes	T178,T30,T179	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T178,T30,T179	Yes	T196,T178,T30	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T123,T196	Yes	T72,T123,T196	OUTPUT
cio_scl_i	Yes	Yes	T101,T199,T200	Yes	T101,T199,T200	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T199,T201,T202	Yes	T199,T201,T202	OUTPUT
cio_sda_i	Yes	Yes	T101,T199,T200	Yes	T101,T199,T200	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T101,T199,T200	Yes	T101,T199,T200	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T89,T199,T182	Yes	T89,T199,T182	OUTPUT
intr_rx_threshold_o	Yes	Yes	T89,T199,T182	Yes	T89,T199,T182	OUTPUT
intr_acq_threshold_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_rx_overflow_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_controller_halt_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_scl_interference_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_sda_interference_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_sda_unstable_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_cmd_complete_o	Yes	Yes	T89,T101,T199	Yes	T89,T101,T199	OUTPUT
intr_tx_stretch_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_tx_threshold_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_acq_stretch_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_unexp_stop_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_host_timeout_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	350	294	84.00
Total Bits 0->1	175	147	84.00
Total Bits 1->0	175	147	84.00

Ports	54	40	74.07
Port Bits	350	294	84.00
Port Bits 0->1	175	147	84.00
Port Bits 1->0	175	147	84.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T120,T193	Yes	T6,T120,T193	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T6,T120,T193	Yes	T6,T120,T193	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T6,T120,T72	Yes	T6,T120,T72	INPUT
tl_o.a_ready	Yes	Yes	T6,T120,T72	Yes	T6,T120,T72	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T193,T89	Yes	T6,T193,T89	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T6,T120,T193	Yes	T6,T120,T72	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T120,*T123,*T194	Yes	T6,T120,T72	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T6,T120,T193	Yes	T6,T120,T72	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T6,*T120,*T193	Yes	T6,T120,T72	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T120,T123,T194	Yes	T6,T120,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T120,*T193	Yes	T6,T120,T193	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T120,T72	Yes	T6,T120,T72	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T123,T195	Yes	T72,T123,T195	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T178,T30,T179	Yes	T178,T30,T179	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T178,T30,T179	Yes	T178,T30,T179	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T123,T195	Yes	T72,T123,T195	OUTPUT
cio_scl_i	Yes	Yes	T6,T193,T198	Yes	T6,T193,T198	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T6,T193,T198	Yes	T6,T193,T198	OUTPUT
cio_sda_i	Yes	Yes	T6,T193,T198	Yes	T6,T193,T198	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T6,T193,T198	Yes	T6,T193,T198	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T6,T193,T89	Yes	T6,T193,T89	OUTPUT
intr_rx_threshold_o	Yes	Yes	T6,T193,T89	Yes	T6,T193,T89	OUTPUT
intr_acq_threshold_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_rx_overflow_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_controller_halt_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_scl_interference_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_sda_interference_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_sda_unstable_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_cmd_complete_o	Yes	Yes	T6,T193,T89	Yes	T6,T193,T89	OUTPUT
intr_tx_stretch_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_tx_threshold_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_acq_stretch_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_unexp_stop_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_host_timeout_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	54	40	74.07
Total Bits	350	294	84.00
Total Bits 0->1	175	147	84.00
Total Bits 1->0	175	147	84.00

Ports	54	40	74.07
Port Bits	350	294	84.00
Port Bits 0->1	175	147	84.00
Port Bits 1->0	175	147	84.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T120,T89,T197	Yes	T120,T89,T197	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T120,T89,T197	Yes	T120,T89,T197	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T120,T72,T123	Yes	T120,T72,T123	INPUT
tl_o.a_ready	Yes	Yes	T120,T72,T123	Yes	T120,T72,T123	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T89,T197,T203	Yes	T89,T197,T203	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T120,T123,T89	Yes	T120,T72,T123	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T120,*T123,*T194	Yes	T120,T72,T123	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T120,T123,T89	Yes	T120,T72,T123	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T120,*T123,*T89	Yes	T120,T72,T123	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T120,T123,T194	Yes	T120,T72,T123	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T120,*T89,*T197	Yes	T120,T89,T197	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T120,T72,T123	Yes	T120,T72,T123	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T123,T178	Yes	T72,T123,T178	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T178,T30,T179	Yes	T178,T30,T179	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T178,T30,T179	Yes	T178,T30,T179	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T123,T178	Yes	T72,T123,T178	OUTPUT
cio_scl_i	Yes	Yes	T197,T203,T204	Yes	T197,T203,T204	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T203,T204,T205	Yes	T203,T204,T205	OUTPUT
cio_sda_i	Yes	Yes	T197,T203,T204	Yes	T197,T203,T204	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T197,T203,T204	Yes	T197,T203,T204	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T89,T203,T204	Yes	T89,T203,T204	OUTPUT
intr_rx_threshold_o	Yes	Yes	T89,T203,T204	Yes	T89,T203,T204	OUTPUT
intr_acq_threshold_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_rx_overflow_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_controller_halt_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_scl_interference_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_sda_interference_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_sda_unstable_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_cmd_complete_o	Yes	Yes	T89,T197,T203	Yes	T89,T197,T203	OUTPUT
intr_tx_stretch_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_tx_threshold_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_acq_stretch_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_unexp_stop_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_host_timeout_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT

*Tests covering at least one bit in the range