Unified Coverage Report :: Module :: csrng

Module : csrng

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70			96.70

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_csrng_0.1/rtl/csrng.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_csrng	96.70			96.70

---

Module Instance : tb.dut.top_earlgrey.u_csrng

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70			96.70

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70			96.70

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : csrng

	Total	Covered	Percent
Totals	65	52	80.00
Total Bits	1790	1731	96.70
Total Bits 0->1	895	866	96.76
Total Bits 1->0	895	865	96.65

Ports	65	52	80.00
Port Bits	1790	1731	96.70
Port Bits 0->1	895	866	96.76
Port Bits 1->0	895	865	96.65

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T129,T72,T140	Yes	T129,T72,T140	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T129,*T72,*T140	Yes	T129,T72,T140	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	INPUT
tl_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_o.a_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T5,*T17,*T58	Yes	T5,T6,T17	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T129,*T72,*T140	Yes	T129,T72,T140	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T129,*T140,*T135	Yes	T129,T140,T135	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
otp_en_csrng_sw_app_read_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T17	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T5,T17,T18	Yes	T5,T6,T17	INPUT
entropy_src_hw_if_o.es_req	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
entropy_src_hw_if_i.es_fips	Yes	Yes	T141,T160,T100	Yes	T129,T140,T135	INPUT
entropy_src_hw_if_i.es_bits[383:0]	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	INPUT
entropy_src_hw_if_i.es_ack	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
cs_aes_halt_i.cs_aes_halt_req	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	INPUT
cs_aes_halt_o.cs_aes_halt_ack	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	OUTPUT
csrng_cmd_i[0].genbits_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
csrng_cmd_i[0].csrng_req_bus[31:0]	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	INPUT
csrng_cmd_i[0].csrng_req_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
csrng_cmd_i[1].genbits_ready	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	INPUT
csrng_cmd_i[1].csrng_req_bus[31:0]	Yes	Yes	T129,T135,T141	Yes	T129,T140,T135	INPUT
csrng_cmd_i[1].csrng_req_valid	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	INPUT
csrng_cmd_o[0].genbits_bus[127:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
csrng_cmd_o[0].genbits_fips	Yes	Yes	T141,T160,T100	Yes	T129,T140,T135	OUTPUT
csrng_cmd_o[0].genbits_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
csrng_cmd_o[0].csrng_rsp_sts[2:0]	No	No		No		OUTPUT
csrng_cmd_o[0].csrng_rsp_ack	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
csrng_cmd_o[0].csrng_req_ready	Yes	Yes	T135,T161,T159	Yes	T135,T161,T159	OUTPUT
csrng_cmd_o[1].genbits_bus[127:0]	Yes	Yes	T129,T140,T135	Yes	T129,T135,T141	OUTPUT
csrng_cmd_o[1].genbits_fips	No	No		Yes	T160,T100,T426	OUTPUT
csrng_cmd_o[1].genbits_valid	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	OUTPUT
csrng_cmd_o[1].csrng_rsp_sts[2:0]	No	No		No		OUTPUT
csrng_cmd_o[1].csrng_rsp_ack	Yes	Yes	T129,T140,T135	Yes	T129,T140,T135	OUTPUT
csrng_cmd_o[1].csrng_req_ready	Yes	Yes	T135,T161,T159	Yes	T135,T161,T159	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T280,T423	Yes	T72,T280,T423	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T280,T28,T30	Yes	T280,T28,T30	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T280,T28,T30	Yes	T280,T28,T30	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T72,T364,T430	Yes	T72,T364,T430	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T280,T423	Yes	T72,T280,T423	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T72,T364,T430	Yes	T72,T364,T430	OUTPUT
intr_cs_cmd_req_done_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_cs_entropy_req_o	Yes	Yes	T89,T378,T379	Yes	T89,T378,T379	OUTPUT
intr_cs_hw_inst_exc_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT
intr_cs_fatal_err_o	Yes	Yes	T89,T182,T183	Yes	T89,T182,T183	OUTPUT

*Tests covering at least one bit in the range