Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	53750267	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	53750267	0	0
T5	260272	17834	0	0
T6	332659	32980	0	0
T17	232171	30578	0	0
T18	700306	0	0	0
T32	93001	12170	0	0
T58	503221	62756	0	0
T73	162299	12769	0	0
T75	232122	30311	0	0
T83	72682	9387	0	0
T144	285046	30992	0	0
T292	0	20692	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	41330975	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	41330975	0	0
T5	260272	13865	0	0
T6	332659	28700	0	0
T17	232171	20915	0	0
T18	700306	0	0	0
T32	93001	8961	0	0
T58	503221	51335	0	0
T73	162299	9013	0	0
T75	232122	20795	0	0
T83	72682	6241	0	0
T144	285046	23594	0	0
T292	0	15620	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	37242649	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	37242649	0	0
T5	260272	10531	0	0
T6	332659	29929	0	0
T17	232171	14795	0	0
T18	700306	39	0	0
T32	93001	5756	0	0
T58	503221	29009	0	0
T73	162299	7082	0	0
T75	232122	14769	0	0
T83	72682	3819	0	0
T144	285046	17365	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	33247396	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	33247396	0	0
T5	260272	10278	0	0
T6	332659	29611	0	0
T17	232171	14407	0	0
T18	700306	39	0	0
T32	93001	5609	0	0
T58	503221	28246	0	0
T73	162299	6839	0	0
T75	232122	14391	0	0
T83	72682	3673	0	0
T144	285046	16922	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	62723	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	62723	0	0
T5	260272	29	0	0
T6	332659	23	0	0
T17	232171	151	0	0
T18	700306	0	0	0
T32	93001	16	0	0
T58	503221	78	0	0
T73	162299	28	0	0
T75	232122	151	0	0
T83	72682	16	0	0
T144	285046	64	0	0
T292	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	62723	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	62723	0	0
T5	260272	29	0	0
T6	332659	23	0	0
T17	232171	151	0	0
T18	700306	0	0	0
T32	93001	16	0	0
T58	503221	78	0	0
T73	162299	28	0	0
T75	232122	151	0	0
T83	72682	16	0	0
T144	285046	64	0	0
T292	0	26	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	50299	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	50299	0	0
T5	260272	25	0	0
T6	332659	20	0	0
T17	232171	95	0	0
T18	700306	0	0	0
T32	93001	13	0	0
T58	503221	75	0	0
T73	162299	26	0	0
T75	232122	95	0	0
T83	72682	13	0	0
T144	285046	59	0	0
T292	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	50299	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	50299	0	0
T5	260272	25	0	0
T6	332659	20	0	0
T17	232171	95	0	0
T18	700306	0	0	0
T32	93001	13	0	0
T58	503221	75	0	0
T73	162299	26	0	0
T75	232122	95	0	0
T83	72682	13	0	0
T144	285046	59	0	0
T292	0	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	12424	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	12424	0	0
T5	260272	4	0	0
T6	332659	3	0	0
T17	232171	56	0	0
T18	700306	0	0	0
T32	93001	3	0	0
T58	503221	3	0	0
T73	162299	2	0	0
T75	232122	56	0	0
T83	72682	3	0	0
T144	285046	5	0	0
T292	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	476135084	12424	0	0
DepthKnown_A	476135084	476031290	0	0
RvalidKnown_A	476135084	476031290	0	0
WreadyKnown_A	476135084	476031290	0	0
gen_passthru_fifo.paramCheckPass	988	988	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	12424	0	0
T5	260272	4	0	0
T6	332659	3	0	0
T17	232171	56	0	0
T18	700306	0	0	0
T32	93001	3	0	0
T58	503221	3	0	0
T73	162299	2	0	0
T75	232122	56	0	0
T83	72682	3	0	0
T144	285046	5	0	0
T292	0	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	476031290	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	700193	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0