Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.81			93.81

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main	93.49			93.49
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon	94.37			94.37

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.49			93.49

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.49			93.49

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.37			94.37

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.37			94.37

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	66	45	68.18
Total Bits	1164	1092	93.81
Total Bits 0->1	582	546	93.81
Total Bits 1->0	582	546	93.81

Ports	66	45	68.18
Port Bits	1164	1092	93.81
Port Bits 0->1	582	546	93.81
Port Bits 1->0	582	546	93.81

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[20:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[27:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T17	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T72,*T145,*T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_valid	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_o.a_ready	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	T231,*T20,T91	Yes	T231,T20,T91	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T231,T20,*T91	Yes	T72,T69,T70	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T231,T20,T91	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T231,T20,T91	Yes	T72,T69,T70	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T20,*T231,*T91	Yes	T20,T22,T23	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T231,T20,T91	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T231,*T20,*T91	Yes	T145,T231,T20	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T20,T30	Yes	T72,T20,T30	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T20,T30	Yes	T72,T20,T30	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T5,T17,T75	Yes	T4,T5,T17	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T5,T17,T18	Yes	T5,T6,T17	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T17	INPUT
sram_otp_key_o.req	Yes	Yes	T69,T70,T231	Yes	T69,T70,T231	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T17,T58,T73	Yes	T6,T17,T83	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T6,T17,T32	Yes	T17,T58,T73	INPUT
sram_otp_key_i.ack	Yes	Yes	T69,T70,T231	Yes	T69,T70,T231	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

	Total	Covered	Percent
Totals	62	39	62.90
Total Bits	1136	1062	93.49
Total Bits 0->1	568	531	93.49
Total Bits 1->0	568	531	93.49

Ports	62	39	62.90
Port Bits	1136	1062	93.49
Port Bits 0->1	568	531	93.49
Port Bits 1->0	568	531	93.49

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[27:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[31:29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[4:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_source[5]	No	No		No		INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[0]	No	No		No		INPUT
ram_tl_i.a_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T17	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T72,T69,T70	Yes	T72,T69,T70	INPUT
regs_tl_i.a_user.cmd_intg[0]	Yes	Yes	*T72,*T145,*T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
regs_tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T145,T20,T91	Yes	T145,T20,T91	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T72,*T145,*T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[18:0]	Yes	Yes	*T72,*T69,*T70	Yes	T72,T69,T70	INPUT
regs_tl_i.a_data[19]	No	No		No		INPUT
regs_tl_i.a_data[23:20]	Yes	Yes	T20	Yes	T20	INPUT
regs_tl_i.a_data[24]	No	No		No		INPUT
regs_tl_i.a_data[31:25]	Yes	Yes	T20	Yes	T20	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	*T145,*T69,*T70	Yes	T145,T69,T70	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T72,*T145,*T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T72,*T145,*T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[1:0]	Yes	Yes	*T20,*T22,*T23	Yes	T20,T22,T23	INPUT
regs_tl_i.a_source[5:2]	No	No		No		INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[0]	No	No		No		INPUT
regs_tl_i.a_size[1]	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[1:0]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T145,T20,T91	Yes	T145,T20,T91	INPUT
regs_tl_i.a_valid	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_o.a_ready	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	*T20,*T146,*T147	Yes	T20,T146,T147	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T20,*T91,*T148	Yes	T72,T69,T70	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T20,T91,T148	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T20,T91,T148	Yes	T72,T69,T70	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T20,*T91,*T148	Yes	T20,T22,T23	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T20,T91,T148	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T20,*T91,*T148	Yes	T145,T20,T91	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T20,T30	Yes	T72,T20,T30	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T20,T30	Yes	T72,T20,T30	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T5,T17,T75	Yes	T4,T5,T17	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T5,T17,T18	Yes	T5,T6,T17	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T17	INPUT
sram_otp_key_o.req	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T17,T58,T73	Yes	T6,T17,T83	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T6,T17,T32	Yes	T17,T58,T73	INPUT
sram_otp_key_i.ack	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

	Total	Covered	Percent
Totals	60	42	70.00
Total Bits	1102	1040	94.37
Total Bits 0->1	551	520	94.37
Total Bits 1->0	551	520	94.37

Ports	60	42	70.00
Port Bits	1102	1040	94.37
Port Bits 0->1	551	520	94.37
Port Bits 1->0	551	520	94.37

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T17,T58	Yes	T5,T17,T58	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
ram_tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[11:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[20:12]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_i.a_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T17	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T17,T58	Yes	T5,T17,T58	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T5,T17,T58	Yes	T5,T17,T58	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[1:0]	Yes	Yes	*T81,*T249,*T250	Yes	T81,T249,T250	OUTPUT
ram_tl_o.d_source[5:2]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T145,T69,T70	Yes	T145,T69,T70	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T145,T69,T70	Yes	T145,T69,T70	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
regs_tl_i.a_valid	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	INPUT
regs_tl_o.a_ready	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	T231,*T20,*T91	Yes	T231,T20,T91	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T231,T20,*T91	Yes	T72,T69,T70	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T231,T20,*T359	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T231,T20,T91	Yes	T72,T69,T70	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[1:0]	Yes	Yes	*T20,*T231,*T91	Yes	T20,T69,T231	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T231,T20,T359	Yes	T72,T145,T69	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T231,*T20,*T91	Yes	T145,T231,T20	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T72,T145,T69	Yes	T72,T145,T69	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T20,T30	Yes	T72,T20,T30	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T20,T30	Yes	T72,T20,T30	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T5,T17,T75	Yes	T4,T5,T17	INPUT
lc_hw_debug_en_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_sram_ifetch_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
sram_otp_key_o.req	Yes	Yes	T231,T91,T148	Yes	T231,T91,T148	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T17,T58,T73	Yes	T6,T17,T83	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T6,T17,T32	Yes	T17,T58,T73	INPUT
sram_otp_key_i.ack	Yes	Yes	T231,T91,T148	Yes	T231,T91,T148	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range