Unified Coverage Report :: Module :: pattgen

Module : pattgen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pattgen_0.1/rtl/pattgen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pattgen	90.00			90.00

---

Module Instance : tb.dut.top_earlgrey.u_pattgen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00			90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pattgen

	Total	Covered	Percent
Totals	35	27	77.14
Total Bits	300	270	90.00
Total Bits 0->1	150	135	90.00
Total Bits 1->0	150	135	90.00

Ports	35	27	77.14
Port Bits	300	270	90.00
Port Bits 0->1	150	135	90.00
Port Bits 1->0	150	135	90.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T119,T317	Yes	T18,T119,T317	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T119,T317	Yes	T18,T119,T317	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19:17]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T18,T119,T72	Yes	T18,T119,T72	INPUT
tl_o.a_ready	Yes	Yes	T18,T119,T72	Yes	T18,T119,T72	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T119,T317	Yes	T18,T119,T317	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T18,T119,T317	Yes	T18,T119,T72	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T18,T20,*T119	Yes	T18,T119,T72	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T119,T317	Yes	T18,T119,T72	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T18,*T20,*T119	Yes	T18,T20,T119	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T18,T20	Yes	T18,T119,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T119,*T317	Yes	T18,T119,T317	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T119,T72	Yes	T18,T119,T72	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T20,T360	Yes	T72,T20,T360	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T20,T360	Yes	T72,T20,T360	OUTPUT
cio_pda0_tx_o	Yes	Yes	T317,T20	Yes	T317,T20	OUTPUT
cio_pcl0_tx_o	Yes	Yes	T18,T317	Yes	T18,T317	OUTPUT
cio_pda1_tx_o	Yes	Yes	T317,T361,T362	Yes	T317,T361,T362	OUTPUT
cio_pcl1_tx_o	Yes	Yes	T18,T317,T361	Yes	T18,T317,T361	OUTPUT
cio_pda0_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pcl0_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pda1_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_pcl1_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_done_ch0_o	Yes	Yes	T119,T317,T124	Yes	T119,T317,T124	OUTPUT
intr_done_ch1_o	Yes	Yes	T119,T317,T124	Yes	T119,T317,T124	OUTPUT

*Tests covering at least one bit in the range