Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	90.13			90.13
tb.dut.top_earlgrey.u_uart1	90.20			90.20
tb.dut.top_earlgrey.u_uart2	90.20			90.20
tb.dut.top_earlgrey.u_uart3	90.26			90.26

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.13			90.13

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.20			90.20

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.26			90.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.59	90.68		87.09			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T126,T69	Yes	T5,T126,T69	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T126,T69	Yes	T5,T126,T69	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T5,T72,T126	Yes	T5,T72,T126	INPUT
tl_o.a_ready	Yes	Yes	T72,T126,T69	Yes	T72,T126,T69	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T126,T173,T352	Yes	T126,T173,T352	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T126,T69,T353	Yes	T72,T126,T69	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T123,*T125,*T354	Yes	T72,T126,T69	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T126,T69,T353	Yes	T72,T126,T69	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T108,*T126,*T69	Yes	T108,T126,T69	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T123,T125,T354	Yes	T72,T126,T69	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T126,*T69,*T353	Yes	T126,T69,T353	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T72,T126,T69	Yes	T72,T126,T69	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T292,T226,T72	Yes	T292,T226,T72	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T123,T28,T30	Yes	T123,T28,T30	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T123,T28,T30	Yes	T123,T28,T30	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T292,T226,T72	Yes	T292,T226,T72	OUTPUT
cio_rx_i	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	INPUT
cio_tx_o	Yes	Yes	T69,T173,T70	Yes	T69,T173,T70	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T353,T173	Yes	T126,T353,T173	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T353,T173	Yes	T126,T353,T173	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	304	274	90.13
Total Bits 0->1	152	137	90.13
Total Bits 1->0	152	137	90.13

Ports	40	32	80.00
Port Bits	304	274	90.13
Port Bits 0->1	152	137	90.13
Port Bits 1->0	152	137	90.13

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T126,T69	Yes	T5,T126,T69	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T126,T69	Yes	T5,T126,T69	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T5,T72,T126	Yes	T5,T72,T126	INPUT
tl_o.a_ready	Yes	Yes	T72,T126,T69	Yes	T72,T126,T69	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T126,T352,T149	Yes	T126,T352,T149	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T126,T69,T353	Yes	T72,T126,T69	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T123,*T125,*T354	Yes	T72,T126,T69	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T126,T69,T353	Yes	T72,T126,T69	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T108,*T126,*T69	Yes	T108,T126,T69	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T123,T125,T354	Yes	T72,T126,T69	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T126,*T69,*T353	Yes	T126,T69,T353	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T72,T126,T69	Yes	T72,T126,T69	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T226,T72,T123	Yes	T226,T72,T123	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T31,T82	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T226,T72,T123	Yes	T226,T72,T123	OUTPUT
cio_rx_i	Yes	Yes	T5,T17,T58	Yes	T5,T6,T17	INPUT
cio_tx_o	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T149,T323	Yes	T126,T149,T323	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T149,T323	Yes	T126,T149,T323	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T149,T323	Yes	T126,T149,T323	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T353,T149	Yes	T126,T353,T149	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T353,T149	Yes	T126,T353,T149	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	40	32	80.00
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T126,T251,T322	Yes	T126,T251,T322	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T126,T251,T322	Yes	T126,T251,T322	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T72,T126,T123	Yes	T72,T126,T123	INPUT
tl_o.a_ready	Yes	Yes	T72,T126,T123	Yes	T72,T126,T123	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T126,T251,T322	Yes	T126,T251,T322	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T126,T123,T251	Yes	T72,T126,T123	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T123,*T194,*T108	Yes	T72,T126,T123	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T126,T123,T251	Yes	T72,T126,T123	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T108,*T126,*T123	Yes	T108,T126,T123	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T123,T194,T108	Yes	T72,T126,T123	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T126,*T251,*T322	Yes	T126,T251,T322	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T72,T126,T123	Yes	T72,T126,T123	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T123,T365	Yes	T72,T123,T365	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T30,T366,T31	Yes	T30,T31,T82	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T30,T31,T82	Yes	T30,T366,T31	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T123,T365	Yes	T72,T123,T365	OUTPUT
cio_rx_i	Yes	Yes	T251,T322,T59	Yes	T251,T322,T59	INPUT
cio_tx_o	Yes	Yes	T251,T322,T367	Yes	T251,T322,T367	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T251,T322	Yes	T126,T251,T322	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T251,T322	Yes	T126,T251,T322	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T251,T322	Yes	T126,T251,T322	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T251,T322	Yes	T126,T251,T322	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T251,T322	Yes	T126,T251,T322	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	306	276	90.20
Total Bits 0->1	153	138	90.20
Total Bits 1->0	153	138	90.20

Ports	40	32	80.00
Port Bits	306	276	90.20
Port Bits 0->1	153	138	90.20
Port Bits 1->0	153	138	90.20

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T72,T126,T173	Yes	T72,T126,T173	INPUT
tl_o.a_ready	Yes	Yes	T72,T126,T173	Yes	T72,T126,T173	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T126,T173,T174	Yes	T72,T126,T173	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T123,*T194,*T108	Yes	T72,T126,T173	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T126,T173,T174	Yes	T72,T126,T173	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T108,*T126,*T173	Yes	T108,T126,T173	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T123,T194,T108	Yes	T72,T126,T173	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T126,*T173,*T174	Yes	T126,T173,T174	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T72,T126,T173	Yes	T72,T126,T173	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T72,T368,T123	Yes	T72,T368,T123	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T123,T30,T31	Yes	T123,T30,T31	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T123,T30,T31	Yes	T123,T30,T31	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T72,T368,T123	Yes	T72,T368,T123	OUTPUT
cio_rx_i	Yes	Yes	T173,T174,T175	Yes	T173,T174,T175	INPUT
cio_tx_o	Yes	Yes	T173,T174,T175	Yes	T173,T174,T175	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
intr_tx_empty_o	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
intr_rx_watermark_o	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
intr_tx_done_o	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
intr_rx_overflow_o	Yes	Yes	T126,T173,T174	Yes	T126,T173,T174	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	32	80.00
Total Bits	308	278	90.26
Total Bits 0->1	154	139	90.26
Total Bits 1->0	154	139	90.26

Ports	40	32	80.00
Port Bits	308	278	90.26
Port Bits 0->1	154	139	90.26
Port Bits 1->0	154	139	90.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T17	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T40,T126,T355	Yes	T40,T126,T355	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T40,T126,T355	Yes	T40,T126,T355	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T5,*T6,*T17	Yes	T5,T6,T17	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T18,*T20,*T81	Yes	T18,T20,T81	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T5,T6,T17	Yes	T5,T6,T17	INPUT
tl_i.a_valid	Yes	Yes	T72,T40,T126	Yes	T72,T40,T126	INPUT
tl_o.a_ready	Yes	Yes	T72,T40,T126	Yes	T72,T40,T126	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T40,T126,T355	Yes	T40,T126,T355	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T40,T126,T123	Yes	T72,T40,T126	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T123,*T194,T108	Yes	T72,T40,T126	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T40,T126,T123	Yes	T72,T40,T126	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[1:0]	Yes	Yes	*T108,*T40,*T126	Yes	T108,T40,T126	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T123,T194,T108	Yes	T72,T40,T126	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T40,*T126,*T355	Yes	T40,T126,T355	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T72,T40,T126	Yes	T72,T40,T126	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T292,T72,T123	Yes	T292,T72,T123	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T28,T30,T31	Yes	T28,T30,T31	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T292,T72,T123	Yes	T292,T72,T123	OUTPUT
cio_rx_i	Yes	Yes	T40,T355,T369	Yes	T40,T355,T369	INPUT
cio_tx_o	Yes	Yes	T40,T355,T369	Yes	T40,T355,T369	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T40,T126,T355	Yes	T40,T126,T355	OUTPUT
intr_tx_empty_o	Yes	Yes	T40,T126,T355	Yes	T40,T126,T355	OUTPUT
intr_rx_watermark_o	Yes	Yes	T40,T126,T355	Yes	T40,T126,T355	OUTPUT
intr_tx_done_o	Yes	Yes	T40,T126,T355	Yes	T40,T126,T355	OUTPUT
intr_rx_overflow_o	Yes	Yes	T40,T126,T355	Yes	T40,T126,T355	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_break_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_timeout_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T126,T191,T192	Yes	T126,T191,T192	OUTPUT

*Tests covering at least one bit in the range