Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.49 77.49

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 77.49 77.49


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.49 77.49


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
77.49 77.49


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 289 52.55
Total Bits 6824 5288 77.49
Total Bits 0->1 3412 2644 77.49
Total Bits 1->0 3412 2644 77.49

Ports 550 289 52.55
Port Bits 6824 5288 77.49
Port Bits 0->1 3412 2644 77.49
Port Bits 1->0 3412 2644 77.49

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_fixed_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host0_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_spi_host1_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
rst_fixed_ni Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
rst_usb_ni Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
rst_spi_host0_ni Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
rst_spi_host1_ni Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
tl_rv_core_ibex__corei_i.d_ready No No No INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[2:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__corei_i.a_source[5:3] No No No INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] No No No INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T17,T75,T106 Yes T17,T75,T106 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0] Yes Yes *T17,*T75,*T107 Yes T17,T75,T107 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__corei_o.d_sink No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[0] No No No OUTPUT
tl_rv_core_ibex__corei_o.d_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T18,T20,T81 Yes T18,T20,T81 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T20,T108,T109 Yes T20,T108,T109 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T20,T108,T55 Yes T20,T108,T55 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cored_i.a_opcode[1] No No No INPUT
tl_rv_core_ibex__cored_i.a_opcode[2] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T17,T75,T110 Yes T17,T75,T110 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0] Yes Yes *T5,*T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cored_o.d_sink No No No OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T5,T17,T18 Yes T5,T6,T17 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T18,T21,T26 Yes T18,T21,T26 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T5,T17,T18 Yes T5,T6,T17 INPUT
tl_rv_dm__sba_i.a_user.instr_type[0] Yes Yes *T5,*T17,*T18 Yes T5,T6,T17 INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1] No No No INPUT
tl_rv_dm__sba_i.a_user.instr_type[3] Yes Yes T5,T17,T18 Yes T5,T6,T17 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T18,T21,T26 Yes T18,T21,T26 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T5,T17,T18 Yes T5,T6,T17 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] No No No INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[0] No No No INPUT
tl_rv_dm__sba_i.a_size[1] Yes Yes T5,T17,T18 Yes T5,T6,T17 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[1:0] No No No INPUT
tl_rv_dm__sba_i.a_opcode[2] Yes Yes T5,T17,T18 Yes T5,T6,T17 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T18,T21,T26 Yes T18,T21,T26 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_rv_dm__sba_o.d_error No No No OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T18,T21,T26 Yes T18,T21,T26 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0] Yes Yes T18,T21,T26 Yes T18,T21,T26 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2] No No No OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3] Yes Yes T18,T21,T26 Yes T18,T21,T26 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6] No No No OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T18,T21,T26 Yes T18,T21,T26 OUTPUT
tl_rv_dm__sba_o.d_sink No No No OUTPUT
tl_rv_dm__sba_o.d_source[5:0] No No No OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[0] No No No OUTPUT
tl_rv_dm__sba_o.d_size[1] Yes Yes T18,T21,T26 Yes T18,T21,T26 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T18,*T21,*T26 Yes T18,T21,T26 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T18,T21,T26 Yes T18,T21,T26 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] No No No OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] No No No OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] No No No OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] No No No OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] No No No OUTPUT
tl_rv_dm__regs_o.a_valid No No No OUTPUT
tl_rv_dm__regs_i.a_ready No No No INPUT
tl_rv_dm__regs_i.d_error No No No INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] No No No INPUT
tl_rv_dm__regs_i.d_data[31:0] No No No INPUT
tl_rv_dm__regs_i.d_sink No No No INPUT
tl_rv_dm__regs_i.d_source[5:0] No No No INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] No No No INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] No No No INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid No No No INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T20,T22,T23 Yes T20,T22,T23 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T20,T22,T23 Yes T20,T22,T23 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T20,T22,T23 Yes T20,T22,T23 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T20,T22,T23 Yes T20,T22,T23 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T20,T22,T23 Yes T20,T22,T23 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[4:0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 OUTPUT
tl_rv_dm__mem_o.a_source[5] No No No OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[0] No No No OUTPUT
tl_rv_dm__mem_o.a_size[1] Yes Yes T20,T22,T23 Yes T20,T22,T23 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0] No No No OUTPUT
tl_rv_dm__mem_o.a_opcode[2] Yes Yes T20,T22,T23 Yes T20,T22,T23 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T20,T22,T23 Yes T20,T22,T23 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T5,T6,T17 Yes T5,T17,T18 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T22,T23,T24 Yes T22,T23,T24 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0] Yes Yes *T20,*T22,*T23 Yes T20,T22,T23 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4] Yes Yes *T20,*T24,*T25 Yes T20,T22,T23 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T5,T6,T17 Yes T5,T17,T18 INPUT
tl_rv_dm__mem_i.d_sink No No No INPUT
tl_rv_dm__mem_i.d_source[4:0] Yes Yes *T22,*T23,*T24 Yes T22,T23,T24 INPUT
tl_rv_dm__mem_i.d_source[5] No No No INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[0] No No No INPUT
tl_rv_dm__mem_i.d_size[1] Yes Yes T20,T24,T25 Yes T20,T22,T23 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T17,T18 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T20,T22,T23 Yes T20,T22,T23 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T21,T69,T70 Yes T21,T69,T70 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T69,T70,T71 Yes T69,T70,T71 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_rom_ctrl__rom_o.a_source[5] No No No OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_rom_ctrl__rom_i.d_error No No No INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5] No No No INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rom_ctrl__rom_i.d_sink No No No INPUT
tl_rom_ctrl__rom_i.d_source[4:0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_rom_ctrl__rom_i.d_source[5] No No No INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[0] No No No INPUT
tl_rom_ctrl__rom_i.d_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] No No No INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[1:0] Yes Yes T72,T111,*T112 Yes T72,T111,T112 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[5:3] Yes Yes *T17,*T113,*T114 Yes T17,T113,T114 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T17,T72,T113 Yes T17,T72,T113 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0] Yes Yes *T17,*T72,*T113 Yes T17,T72,T113 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3] Yes Yes T17,T72,T113 Yes T17,T72,T113 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[0] Yes Yes *T72,*T111,*T112 Yes T72,T111,T112 OUTPUT
tl_rom_ctrl__regs_o.a_data[31:1] No No No OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T17,T72,T113 Yes T17,T72,T113 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[1] Yes Yes *T17,*T72,*T113 Yes T17,T72,T113 OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2] No No No OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_size[1] Yes Yes T17,T72,T113 Yes T17,T72,T113 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0] No No No OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2] Yes Yes T17,T113,T114 Yes T17,T113,T114 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T17,T72,T113 Yes T17,T72,T113 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T17,T72,T113 Yes T17,T72,T113 INPUT
tl_rom_ctrl__regs_i.d_error No No No INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T113,T115,T116 Yes T113,T115,T116 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[0] No No Yes T72,T111,T112 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1] No Yes *T72,*T111,*T112 No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4] Yes Yes T17,T113,T114 Yes T17,T72,T113 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T113,T115,T116 Yes T72,T113,T115 INPUT
tl_rom_ctrl__regs_i.d_sink No No No INPUT
tl_rom_ctrl__regs_i.d_source[0] No No No INPUT
tl_rom_ctrl__regs_i.d_source[1] Yes Yes *T17,*T113,*T114 Yes T17,T72,T113 INPUT
tl_rom_ctrl__regs_i.d_source[5:2] No No No INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[0] No No No INPUT
tl_rom_ctrl__regs_i.d_size[1] Yes Yes T17,T113,T114 Yes T17,T72,T113 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T17,*T113,*T114 Yes T17,T113,T114 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T17,T72,T113 Yes T17,T72,T113 INPUT
tl_peri_o.d_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_peri_o.a_user.instr_type[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_peri_o.a_user.instr_type[2:1] No No No OUTPUT
tl_peri_o.a_user.instr_type[3] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes T18,*T20,*T81 Yes T18,T20,T81 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[0] Yes Yes *T18,*T20,*T81 Yes T18,T20,T81 OUTPUT
tl_peri_o.a_opcode[1] No No No OUTPUT
tl_peri_o.a_opcode[2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_peri_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_peri_i.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_peri_i.d_error Yes Yes T17,T117,T118 Yes T17,T117,T118 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_peri_i.d_user.rsp_intg[5:0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_peri_i.d_user.rsp_intg[6] No No No INPUT
tl_peri_i.d_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_peri_i.d_sink No No No INPUT
tl_peri_i.d_source[5:0] Yes Yes T18,*T20,*T81 Yes T18,T20,T81 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_spi_host0_o.d_ready Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0] Yes Yes *T119,*T120,*T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_user.instr_type[0] Yes Yes *T119,*T120,*T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host0_o.a_user.instr_type[3] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[1:0] Yes Yes *T20,*T119,*T120 Yes T20,T119,T120 OUTPUT
tl_spi_host0_o.a_source[5:2] No No No OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[0] No No No OUTPUT
tl_spi_host0_o.a_size[1] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[0] Yes Yes *T39,*T121,*T122 Yes T39,T121,T122 OUTPUT
tl_spi_host0_o.a_opcode[1] No No No OUTPUT
tl_spi_host0_o.a_opcode[2] Yes Yes T119,T120,T37 Yes T119,T120,T37 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T119,T120,T72 Yes T119,T120,T72 INPUT
tl_spi_host0_i.d_error No No No INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T119,T120,T37 Yes T119,T120,T37 INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0] Yes Yes T119,T120,T37 Yes T119,T120,T72 INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4] Yes Yes T120,T20,*T123 Yes T119,T120,T72 INPUT
tl_spi_host0_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T119,T120,T37 Yes T119,T120,T37 INPUT
tl_spi_host0_i.d_sink No No No INPUT
tl_spi_host0_i.d_source[1:0] Yes Yes *T20,*T120,*T37 Yes T20,T119,T120 INPUT
tl_spi_host0_i.d_source[5:2] No No No INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[0] No No No INPUT
tl_spi_host0_i.d_size[1] Yes Yes T120,T20,T123 Yes T119,T120,T72 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T119,*T120,*T37 Yes T119,T120,T37 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T119,T120,T72 Yes T119,T120,T72 INPUT
tl_spi_host1_o.d_ready Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_o.a_user.instr_type[0] Yes Yes *T119,*T120,*T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_spi_host1_o.a_user.instr_type[3] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[1:0] Yes Yes *T20,*T119,*T120 Yes T20,T119,T120 OUTPUT
tl_spi_host1_o.a_source[5:2] No No No OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[0] No No No OUTPUT
tl_spi_host1_o.a_size[1] Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[1:0] No No No OUTPUT
tl_spi_host1_o.a_opcode[2] Yes Yes T119,T120,T124 Yes T119,T120,T124 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T119,T120,T72 Yes T119,T120,T72 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T119,T120,T72 Yes T119,T120,T72 INPUT
tl_spi_host1_i.d_error No No No INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T119,T120,T124 Yes T119,T120,T124 INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0] Yes Yes T119,T120,T124 Yes T119,T120,T72 INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4] Yes Yes T120,T20,T125 Yes T119,T120,T72 INPUT
tl_spi_host1_i.d_user.rsp_intg[6] No No No INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T119,T120,T124 Yes T119,T120,T124 INPUT
tl_spi_host1_i.d_sink No No No INPUT
tl_spi_host1_i.d_source[1:0] Yes Yes *T20,*T119,*T120 Yes T20,T119,T120 INPUT
tl_spi_host1_i.d_source[5:2] No No No INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[0] No No No INPUT
tl_spi_host1_i.d_size[1] Yes Yes T120,T20,T125 Yes T119,T120,T72 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T119,*T120,*T124 Yes T119,T120,T124 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T119,T120,T72 Yes T119,T120,T72 INPUT
tl_usbdev_o.d_ready Yes Yes T120,T72,T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T120,T72,T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T120,T72,T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_o.a_user.instr_type[0] Yes Yes *T120,*T72,*T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_o.a_user.instr_type[2:1] No No No OUTPUT
tl_usbdev_o.a_user.instr_type[3] Yes Yes T120,T72,T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T120,T72,T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T120,T72,T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[1:0] Yes Yes *T108,*T120,*T126 Yes T108,T120,T126 OUTPUT
tl_usbdev_o.a_source[5:2] No No No OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[0] No No No OUTPUT
tl_usbdev_o.a_size[1] Yes Yes T120,T72,T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[1:0] No No No OUTPUT
tl_usbdev_o.a_opcode[2] Yes Yes T120,T126,T43 Yes T120,T126,T43 OUTPUT
tl_usbdev_o.a_valid Yes Yes T120,T72,T126 Yes T120,T72,T126 OUTPUT
tl_usbdev_i.a_ready Yes Yes T120,T72,T126 Yes T120,T72,T126 INPUT
tl_usbdev_i.d_error No No No INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T120,T126,T43 Yes T120,T126,T43 INPUT
tl_usbdev_i.d_user.rsp_intg[1:0] Yes Yes T120,T126,T43 Yes T120,T126,T43 INPUT
tl_usbdev_i.d_user.rsp_intg[3:2] No No No INPUT
tl_usbdev_i.d_user.rsp_intg[5:4] Yes Yes T120,T127,T45 Yes T120,T72,T126 INPUT
tl_usbdev_i.d_user.rsp_intg[6] No No No INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T120,T72,T126 Yes T120,T126,T43 INPUT
tl_usbdev_i.d_sink No No No INPUT
tl_usbdev_i.d_source[1:0] Yes Yes *T108,*T120,*T126 Yes T108,T120,T126 INPUT
tl_usbdev_i.d_source[5:2] No No No INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[0] No No No INPUT
tl_usbdev_i.d_size[1] Yes Yes T120,T127,T45 Yes T120,T72,T126 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T120,*T72,*T126 Yes T120,T126,T43 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T120,T72,T126 Yes T120,T72,T126 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1] No No No OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[1] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_source[5:2] No No No OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__core_o.a_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__core_o.a_opcode[2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T4,T5,T6 Yes T4,T5,T17 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6] No No No INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T5,T6,T17 Yes T5,T17,T58 INPUT
tl_flash_ctrl__core_i.d_sink No No No INPUT
tl_flash_ctrl__core_i.d_source[0] No No No INPUT
tl_flash_ctrl__core_i.d_source[1] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__core_i.d_source[5:2] No No No INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[0] No No No INPUT
tl_flash_ctrl__core_i.d_size[1] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] No No No OUTPUT
tl_flash_ctrl__prim_o.a_valid No No No OUTPUT
tl_flash_ctrl__prim_i.a_ready No No No INPUT
tl_flash_ctrl__prim_i.d_error No No No INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] No No No INPUT
tl_flash_ctrl__prim_i.d_data[31:0] No No No INPUT
tl_flash_ctrl__prim_i.d_sink No No No INPUT
tl_flash_ctrl__prim_i.d_source[5:0] No No No INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] No No No INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid No No No INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_source[1] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_source[5] No No No OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0] No No No OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T4,T5,T6 Yes T4,T5,T17 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3] No No No INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5] No No No INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__mem_i.d_sink No No No INPUT
tl_flash_ctrl__mem_i.d_source[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__mem_i.d_source[1] No No No INPUT
tl_flash_ctrl__mem_i.d_source[4:2] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__mem_i.d_source[5] No No No INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[0] No No No INPUT
tl_flash_ctrl__mem_i.d_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] No No No INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_hmac_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T32,T83,T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T32,T83,T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_user.instr_type[0] Yes Yes *T32,*T83,*T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_hmac_o.a_user.instr_type[3] Yes Yes T32,T83,T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T32,T83,T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T32,T83,T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[0] No No No OUTPUT
tl_hmac_o.a_source[1] Yes Yes *T32,*T83,*T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_source[5:2] No No No OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[0] No No No OUTPUT
tl_hmac_o.a_size[1] Yes Yes T32,T83,T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[0] Yes Yes *T32,*T83,*T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_opcode[1] No No No OUTPUT
tl_hmac_o.a_opcode[2] Yes Yes T32,T83,T128 Yes T32,T83,T128 OUTPUT
tl_hmac_o.a_valid Yes Yes T32,T83,T128 Yes T32,T83,T128 OUTPUT
tl_hmac_i.a_ready Yes Yes T32,T83,T128 Yes T32,T83,T128 INPUT
tl_hmac_i.d_error No No No INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T32,T83,T128 Yes T32,T83,T128 INPUT
tl_hmac_i.d_user.rsp_intg[1:0] Yes Yes T32,T83,T128 Yes T32,T83,T128 INPUT
tl_hmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_hmac_i.d_user.rsp_intg[5:4] Yes Yes T32,T83,T128 Yes T32,T83,T128 INPUT
tl_hmac_i.d_user.rsp_intg[6] No No No INPUT
tl_hmac_i.d_data[31:0] Yes Yes T32,T83,T128 Yes T32,T83,T128 INPUT
tl_hmac_i.d_sink No No No INPUT
tl_hmac_i.d_source[0] No No No INPUT
tl_hmac_i.d_source[1] Yes Yes *T32,*T83,*T128 Yes T32,T83,T128 INPUT
tl_hmac_i.d_source[5:2] No No No INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[0] No No No INPUT
tl_hmac_i.d_size[1] Yes Yes T32,T83,T128 Yes T32,T83,T128 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T32,*T83,*T128 Yes T32,T83,T128 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T32,T83,T128 Yes T32,T83,T128 INPUT
tl_kmac_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T18,T119,T72 Yes T18,T119,T72 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T18,T58,T129 Yes T18,T58,T129 OUTPUT
tl_kmac_o.a_user.instr_type[0] Yes Yes *T18,*T58,*T129 Yes T18,T58,T129 OUTPUT
tl_kmac_o.a_user.instr_type[2:1] No No No OUTPUT
tl_kmac_o.a_user.instr_type[3] Yes Yes T18,T58,T129 Yes T18,T58,T129 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T18,T119,T72 Yes T18,T119,T72 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T18,T58,T129 Yes T18,T58,T129 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[1:0] Yes Yes *T18,*T20,*T58 Yes T18,T20,T58 OUTPUT
tl_kmac_o.a_source[5:2] No No No OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[0] No No No OUTPUT
tl_kmac_o.a_size[1] Yes Yes T18,T58,T129 Yes T18,T58,T129 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[0] Yes Yes *T130,*T131,*T132 Yes T130,T131,T132 OUTPUT
tl_kmac_o.a_opcode[1] No No No OUTPUT
tl_kmac_o.a_opcode[2] Yes Yes T18,T58,T129 Yes T18,T58,T129 OUTPUT
tl_kmac_o.a_valid Yes Yes T18,T58,T129 Yes T18,T58,T129 OUTPUT
tl_kmac_i.a_ready Yes Yes T18,T58,T129 Yes T18,T58,T129 INPUT
tl_kmac_i.d_error No No No INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T18,T58,T129 Yes T18,T58,T129 INPUT
tl_kmac_i.d_user.rsp_intg[1:0] Yes Yes T18,T58,T129 Yes T18,T58,T129 INPUT
tl_kmac_i.d_user.rsp_intg[3:2] No No No INPUT
tl_kmac_i.d_user.rsp_intg[5:4] Yes Yes T18,T58,T133 Yes T18,T58,T129 INPUT
tl_kmac_i.d_user.rsp_intg[6] No No No INPUT
tl_kmac_i.d_data[31:0] Yes Yes T18,T58,T129 Yes T18,T58,T119 INPUT
tl_kmac_i.d_sink No No No INPUT
tl_kmac_i.d_source[1:0] Yes Yes *T18,*T20,*T58 Yes T18,T20,T58 INPUT
tl_kmac_i.d_source[5:2] No No No INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[0] No No No INPUT
tl_kmac_i.d_size[1] Yes Yes T18,T58,T133 Yes T18,T58,T129 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T18,*T58,*T129 Yes T18,T58,T119 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T18,T58,T129 Yes T18,T58,T129 INPUT
tl_aes_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T129,T134,T72 Yes T129,T134,T72 OUTPUT
tl_aes_o.a_user.cmd_intg[0] Yes Yes *T129,*T134,*T72 Yes T129,T134,T72 OUTPUT
tl_aes_o.a_user.cmd_intg[1] No No No OUTPUT
tl_aes_o.a_user.cmd_intg[6:2] Yes Yes T129,T134,T135 Yes T129,T134,T135 OUTPUT
tl_aes_o.a_user.instr_type[0] Yes Yes *T129,*T134,*T72 Yes T129,T134,T72 OUTPUT
tl_aes_o.a_user.instr_type[2:1] No No No OUTPUT
tl_aes_o.a_user.instr_type[3] Yes Yes T129,T134,T72 Yes T129,T134,T72 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T129,T134,T72 Yes T129,T134,T72 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T129,T134,T72 Yes T129,T134,T72 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[0] No No No OUTPUT
tl_aes_o.a_source[1] Yes Yes *T129,*T134,*T72 Yes T129,T134,T72 OUTPUT
tl_aes_o.a_source[5:2] No No No OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[0] No No No OUTPUT
tl_aes_o.a_size[1] Yes Yes T129,T134,T72 Yes T129,T134,T72 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[1:0] No No No OUTPUT
tl_aes_o.a_opcode[2] Yes Yes T129,T134,T135 Yes T129,T134,T135 OUTPUT
tl_aes_o.a_valid Yes Yes T129,T134,T72 Yes T129,T134,T72 OUTPUT
tl_aes_i.a_ready Yes Yes T129,T134,T72 Yes T129,T134,T72 INPUT
tl_aes_i.d_error No No No INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T129,T134,T135 Yes T129,T134,T135 INPUT
tl_aes_i.d_user.rsp_intg[1:0] Yes Yes T129,T134,T135 Yes T129,T134,T72 INPUT
tl_aes_i.d_user.rsp_intg[3:2] No No No INPUT
tl_aes_i.d_user.rsp_intg[5:4] Yes Yes T136,T137,*T138 Yes T129,T134,T72 INPUT
tl_aes_i.d_user.rsp_intg[6] No No No INPUT
tl_aes_i.d_data[31:0] Yes Yes T134,T135,T139 Yes T129,T134,T72 INPUT
tl_aes_i.d_sink No No No INPUT
tl_aes_i.d_source[0] No No No INPUT
tl_aes_i.d_source[1] Yes Yes *T129,*T134,*T72 Yes T129,T134,T72 INPUT
tl_aes_i.d_source[5:2] No No No INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[0] No No No INPUT
tl_aes_i.d_size[1] Yes Yes T136,T137,T138 Yes T129,T134,T72 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T129,*T134,*T135 Yes T129,T134,T135 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T129,T134,T72 Yes T129,T134,T72 INPUT
tl_entropy_src_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_o.a_user.instr_type[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1] No No No OUTPUT
tl_entropy_src_o.a_user.instr_type[3] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[0] No No No OUTPUT
tl_entropy_src_o.a_source[1] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_o.a_source[5:2] No No No OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[0] No No No OUTPUT
tl_entropy_src_o.a_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[1:0] No No No OUTPUT
tl_entropy_src_o.a_opcode[2] Yes Yes T129,T140,T69 Yes T129,T140,T69 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_entropy_src_i.d_error No No No INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T129,T140,T135 Yes T129,T140,T135 INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2] No No No INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4] Yes Yes *T5,*T17,*T58 Yes T5,T6,T17 INPUT
tl_entropy_src_i.d_user.rsp_intg[6] No No No INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_entropy_src_i.d_sink No No No INPUT
tl_entropy_src_i.d_source[0] No No No INPUT
tl_entropy_src_i.d_source[1] Yes Yes *T5,*T17,*T58 Yes T5,T6,T17 INPUT
tl_entropy_src_i.d_source[5:2] No No No INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[0] No No No INPUT
tl_entropy_src_i.d_size[1] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T129,*T140,*T135 Yes T129,T140,T69 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_csrng_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_csrng_o.a_user.instr_type[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_csrng_o.a_user.instr_type[2:1] No No No OUTPUT
tl_csrng_o.a_user.instr_type[3] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[0] No No No OUTPUT
tl_csrng_o.a_source[1] Yes Yes *T129,*T72,*T140 Yes T129,T72,T140 OUTPUT
tl_csrng_o.a_source[5:2] No No No OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[0] No No No OUTPUT
tl_csrng_o.a_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[1:0] No No No OUTPUT
tl_csrng_o.a_opcode[2] Yes Yes T129,T140,T135 Yes T129,T140,T135 OUTPUT
tl_csrng_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_csrng_i.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_csrng_i.d_error No No No INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T129,T140,T135 Yes T129,T140,T135 INPUT
tl_csrng_i.d_user.rsp_intg[1:0] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_csrng_i.d_user.rsp_intg[3:2] No No No INPUT
tl_csrng_i.d_user.rsp_intg[5:4] Yes Yes *T5,*T17,*T58 Yes T5,T6,T17 INPUT
tl_csrng_i.d_user.rsp_intg[6] No No No INPUT
tl_csrng_i.d_data[31:0] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_csrng_i.d_sink No No No INPUT
tl_csrng_i.d_source[0] No No No INPUT
tl_csrng_i.d_source[1] Yes Yes *T129,*T72,*T140 Yes T129,T72,T140 INPUT
tl_csrng_i.d_source[5:2] No No No INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[0] No No No INPUT
tl_csrng_i.d_size[1] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T129,*T140,*T135 Yes T129,T140,T135 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_edn0_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn0_o.a_user.cmd_intg[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_edn0_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_edn0_o.a_user.instr_type[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_edn0_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn0_o.a_user.instr_type[3] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[0] No No No OUTPUT
tl_edn0_o.a_source[1] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_edn0_o.a_source[5:2] No No No OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[0] No No No OUTPUT
tl_edn0_o.a_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[1:0] No No No OUTPUT
tl_edn0_o.a_opcode[2] Yes Yes T129,T140,T135 Yes T129,T140,T135 OUTPUT
tl_edn0_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_edn0_i.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_edn0_i.d_error No No No INPUT
tl_edn0_i.d_user.data_intg[0] Yes Yes *T129,*T140,*T135 Yes T129,T140,T135 INPUT
tl_edn0_i.d_user.data_intg[1] No No No INPUT
tl_edn0_i.d_user.data_intg[6:2] Yes Yes T129,T140,T135 Yes T129,T140,T135 INPUT
tl_edn0_i.d_user.rsp_intg[1:0] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_edn0_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn0_i.d_user.rsp_intg[5:4] Yes Yes *T5,*T17,*T58 Yes T5,T6,T17 INPUT
tl_edn0_i.d_user.rsp_intg[6] No No No INPUT
tl_edn0_i.d_data[31:0] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_edn0_i.d_sink No No No INPUT
tl_edn0_i.d_source[0] No No No INPUT
tl_edn0_i.d_source[1] Yes Yes *T5,*T17,*T58 Yes T5,T6,T17 INPUT
tl_edn0_i.d_source[5:2] No No No INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[0] No No No INPUT
tl_edn0_i.d_size[1] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T129,*T140,*T135 Yes T129,T140,T135 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_edn1_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_user.cmd_intg[0] Yes Yes *T129,*T72,*T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_user.cmd_intg[1] No No No OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_user.instr_type[0] Yes Yes *T129,*T72,*T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_user.instr_type[2:1] No No No OUTPUT
tl_edn1_o.a_user.instr_type[3] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[0] No No No OUTPUT
tl_edn1_o.a_source[1] Yes Yes *T129,*T72,*T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_source[5:2] No No No OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[0] No No No OUTPUT
tl_edn1_o.a_size[1] Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[1:0] No No No OUTPUT
tl_edn1_o.a_opcode[2] Yes Yes T129,T140,T135 Yes T129,T140,T135 OUTPUT
tl_edn1_o.a_valid Yes Yes T129,T72,T140 Yes T129,T72,T140 OUTPUT
tl_edn1_i.a_ready Yes Yes T129,T72,T140 Yes T129,T72,T140 INPUT
tl_edn1_i.d_error No No No INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T129,T140,T135 Yes T129,T140,T135 INPUT
tl_edn1_i.d_user.rsp_intg[1:0] Yes Yes T129,T140,T135 Yes T129,T72,T140 INPUT
tl_edn1_i.d_user.rsp_intg[3:2] No No No INPUT
tl_edn1_i.d_user.rsp_intg[5:4] Yes Yes T141,*T142,*T143 Yes T129,T72,T140 INPUT
tl_edn1_i.d_user.rsp_intg[6] No No No INPUT
tl_edn1_i.d_data[31:0] Yes Yes T129,T140,T135 Yes T129,T72,T140 INPUT
tl_edn1_i.d_sink No No No INPUT
tl_edn1_i.d_source[0] No No No INPUT
tl_edn1_i.d_source[1] Yes Yes *T129,*T72,*T140 Yes T129,T72,T140 INPUT
tl_edn1_i.d_source[5:2] No No No INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[0] No No No INPUT
tl_edn1_i.d_size[1] Yes Yes T141,T142,T143 Yes T129,T72,T140 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T129,*T140,*T135 Yes T129,T140,T135 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T129,T72,T140 Yes T129,T72,T140 INPUT
tl_rv_plic_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T6,T17,T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T6,T17,T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_o.a_user.instr_type[0] Yes Yes *T6,*T17,*T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_plic_o.a_user.instr_type[3] Yes Yes T6,T17,T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T6,T17,T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T6,T17,T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[1:0] Yes Yes *T20,*T6,*T17 Yes T20,T6,T17 OUTPUT
tl_rv_plic_o.a_source[5:2] No No No OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[0] No No No OUTPUT
tl_rv_plic_o.a_size[1] Yes Yes T6,T17,T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[1:0] No No No OUTPUT
tl_rv_plic_o.a_opcode[2] Yes Yes T6,T17,T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T6,T17,T32 Yes T6,T17,T32 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T6,T17,T32 Yes T6,T17,T32 INPUT
tl_rv_plic_i.d_error No No No INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T6,T17,T75 Yes T6,T17,T75 INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0] Yes Yes T6,T17,T32 Yes T6,T17,T32 INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4] Yes Yes T17,T75,T144 Yes T6,T17,T32 INPUT
tl_rv_plic_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T6,T17,T32 Yes T6,T17,T32 INPUT
tl_rv_plic_i.d_sink No No No INPUT
tl_rv_plic_i.d_source[1:0] Yes Yes *T20,*T6,*T17 Yes T20,T6,T17 INPUT
tl_rv_plic_i.d_source[5:2] No No No INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[0] No No No INPUT
tl_rv_plic_i.d_size[1] Yes Yes T17,T75,T144 Yes T6,T17,T32 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T6,*T17,*T32 Yes T6,T17,T32 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T6,T17,T32 Yes T6,T17,T32 INPUT
tl_otbn_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T18,T129,T119 Yes T18,T129,T119 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T18,T129,T119 Yes T18,T129,T119 OUTPUT
tl_otbn_o.a_user.instr_type[0] Yes Yes *T18,*T129,*T119 Yes T18,T129,T119 OUTPUT
tl_otbn_o.a_user.instr_type[2:1] No No No OUTPUT
tl_otbn_o.a_user.instr_type[3] Yes Yes T18,T129,T119 Yes T18,T129,T119 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T18,T129,T119 Yes T18,T129,T119 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T18,T129,T119 Yes T18,T129,T119 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[1:0] Yes Yes *T18,*T20,*T81 Yes T18,T20,T81 OUTPUT
tl_otbn_o.a_source[5:2] No No No OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[0] No No No OUTPUT
tl_otbn_o.a_size[1] Yes Yes T18,T129,T119 Yes T18,T129,T119 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[1:0] No No No OUTPUT
tl_otbn_o.a_opcode[2] Yes Yes T18,T129,T119 Yes T18,T129,T119 OUTPUT
tl_otbn_o.a_valid Yes Yes T18,T129,T119 Yes T18,T129,T119 OUTPUT
tl_otbn_i.a_ready Yes Yes T18,T129,T119 Yes T18,T129,T119 INPUT
tl_otbn_i.d_error No No No INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T18,T129,T119 Yes T18,T129,T119 INPUT
tl_otbn_i.d_user.rsp_intg[1:0] Yes Yes T18,T129,T119 Yes T18,T129,T119 INPUT
tl_otbn_i.d_user.rsp_intg[3:2] No No No INPUT
tl_otbn_i.d_user.rsp_intg[5:4] Yes Yes T18,T129,T140 Yes T18,T129,T119 INPUT
tl_otbn_i.d_user.rsp_intg[6] No No No INPUT
tl_otbn_i.d_data[31:0] Yes Yes T18,T129,T119 Yes T18,T129,T119 INPUT
tl_otbn_i.d_sink No No No INPUT
tl_otbn_i.d_source[1:0] Yes Yes *T18,*T20,*T81 Yes T18,T20,T81 INPUT
tl_otbn_i.d_source[5:2] No No No INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[0] No No No INPUT
tl_otbn_i.d_size[1] Yes Yes T18,T129,T140 Yes T18,T129,T119 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T18,*T129,*T119 Yes T18,T129,T119 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T18,T129,T119 Yes T18,T129,T119 INPUT
tl_keymgr_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T5,T58,T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_user.cmd_intg[0] Yes Yes *T5,*T58,*T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_user.cmd_intg[1] No No No OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2] Yes Yes T5,T58,T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_user.instr_type[0] Yes Yes *T5,*T58,*T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_user.instr_type[2:1] No No No OUTPUT
tl_keymgr_o.a_user.instr_type[3] Yes Yes T5,T58,T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T5,T58,T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T5,T58,T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[0] No No No OUTPUT
tl_keymgr_o.a_source[1] Yes Yes *T5,*T58,*T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_source[5:2] No No No OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[0] No No No OUTPUT
tl_keymgr_o.a_size[1] Yes Yes T5,T58,T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[1:0] No No No OUTPUT
tl_keymgr_o.a_opcode[2] Yes Yes T5,T58,T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_o.a_valid Yes Yes T5,T58,T129 Yes T5,T58,T129 OUTPUT
tl_keymgr_i.a_ready Yes Yes T5,T58,T129 Yes T5,T58,T129 INPUT
tl_keymgr_i.d_error No No No INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T5,T58,T129 Yes T5,T58,T129 INPUT
tl_keymgr_i.d_user.rsp_intg[1:0] Yes Yes T5,T58,T129 Yes T5,T58,T129 INPUT
tl_keymgr_i.d_user.rsp_intg[3:2] No No No INPUT
tl_keymgr_i.d_user.rsp_intg[5:4] Yes Yes T5,T58,T133 Yes T5,T58,T129 INPUT
tl_keymgr_i.d_user.rsp_intg[6] No No No INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T5,T58,T129 Yes T5,T58,T129 INPUT
tl_keymgr_i.d_sink No No No INPUT
tl_keymgr_i.d_source[0] No No No INPUT
tl_keymgr_i.d_source[1] Yes Yes *T5,*T58,*T129 Yes T5,T58,T129 INPUT
tl_keymgr_i.d_source[5:2] No No No INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[0] No No No INPUT
tl_keymgr_i.d_size[1] Yes Yes T5,T58,T133 Yes T5,T58,T129 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T5,*T58,*T129 Yes T5,T58,T129 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T5,T58,T129 Yes T5,T58,T129 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0] No No No OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cfg_i.d_error No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T6,T17,T32 Yes T6,T17,T32 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[1:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6] No No No INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T6,T17,T32 Yes T6,T17,T32 INPUT
tl_rv_core_ibex__cfg_i.d_sink No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[1] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2] No No No INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[0] No No No INPUT
tl_rv_core_ibex__cfg_i.d_size[1] Yes Yes T5,T17,T58 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T72,T69,T70 Yes T72,T69,T70 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0] Yes Yes *T72,*T145,*T69 Yes T72,T145,T69 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2] Yes Yes T145,T20,T91 Yes T145,T20,T91 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0] Yes Yes *T72,*T145,*T69 Yes T72,T145,T69 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3] Yes Yes T72,T145,T69 Yes T72,T145,T69 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[18:0] Yes Yes *T72,*T69,*T70 Yes T72,T69,T70 OUTPUT
tl_sram_ctrl_main__regs_o.a_data[19] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_data[23:20] Yes Yes T20 Yes T20 OUTPUT
tl_sram_ctrl_main__regs_o.a_data[24] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:25] Yes Yes T20 Yes T20 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T72,T145,T69 Yes T72,T145,T69 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1:0] Yes Yes *T20,*T22,*T23 Yes T20,T22,T23 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1] Yes Yes T72,T145,T69 Yes T72,T145,T69 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0] No No No OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2] Yes Yes T145,T20,T91 Yes T145,T20,T91 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T72,T145,T69 Yes T72,T145,T69 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T72,T145,T69 Yes T72,T145,T69 INPUT
tl_sram_ctrl_main__regs_i.d_error No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0] Yes Yes *T20,*T146,*T147 Yes T20,T146,T147 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0] Yes Yes T20,*T91,*T148 Yes T72,T69,T70 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4] Yes Yes T20,T91,T148 Yes T72,T145,T69 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T20,T91,T148 Yes T72,T69,T70 INPUT
tl_sram_ctrl_main__regs_i.d_sink No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[1:0] Yes Yes *T20,*T91,*T148 Yes T20,T22,T23 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2] No No No INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__regs_i.d_size[1] Yes Yes T20,T91,T148 Yes T72,T145,T69 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T20,*T91,*T148 Yes T145,T20,T91 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T72,T145,T69 Yes T72,T145,T69 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1] No No No OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2] Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T4,T5,T6 Yes T4,T5,T17 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3] No No No INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6] No No No INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_sram_ctrl_main__ram_i.d_sink No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_sram_ctrl_main__ram_i.d_source[5] No No No INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[0] No No No INPUT
tl_sram_ctrl_main__ram_i.d_size[1] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%