Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : pwrmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.64 92.64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pwrmgr_aon 92.64 92.64



Module Instance : tb.dut.top_earlgrey.u_pwrmgr_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.64 92.64


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.64 92.64


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.59 90.68 87.09 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : pwrmgr
TotalCoveredPercent
Totals 84 75 89.29
Total Bits 462 428 92.64
Total Bits 0->1 231 214 92.64
Total Bits 1->0 231 214 92.64

Ports 84 75 89.29
Port Bits 462 428 92.64
Port Bits 0->1 231 214 92.64
Port Bits 1->0 231 214 92.64

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_slow_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_slow_ni Yes Yes T4,T18,T33 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T18,T33 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T4,T18,T73 Yes T4,T5,T6 INPUT
clk_lc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_lc_ni Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
clk_esc_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_esc_ni Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T73,T144,T292 Yes T73,T144,T292 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T73,T144,T292 Yes T73,T144,T292 INPUT
tl_i.a_mask[3:0] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_address[21:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T5,*T6,*T17 Yes T5,T6,T17 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T18,*T20,*T81 Yes T18,T20,T81 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T55,T56,T57 Yes T55,T56,T57 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[0] Yes Yes *T18,*T20,*T81 Yes T18,T20,T81 INPUT
tl_i.a_opcode[1] No No No INPUT
tl_i.a_opcode[2] Yes Yes T5,T6,T17 Yes T5,T6,T17 INPUT
tl_i.a_valid Yes Yes T73,T144,T292 Yes T73,T144,T292 INPUT
tl_o.a_ready Yes Yes T73,T144,T292 Yes T73,T144,T292 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T73,T144,T292 Yes T73,T144,T292 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T73,T144,T292 Yes T73,T144,T292 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T356,*T357,*T358 Yes T73,T144,T292 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T73,T144,T292 Yes T73,T144,T292 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[0] No No No OUTPUT
tl_o.d_source[1] Yes Yes *T73,*T144,*T292 Yes T73,T144,T292 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T356,T357,T358 Yes T73,T144,T292 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T73,*T144,*T292 Yes T73,T144,T292 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T73,T144,T292 Yes T73,T144,T292 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T73,T129,T110 Yes T73,T129,T110 INPUT
alert_rx_i[0].ping_n Yes Yes T30,T31,T82 Yes T30,T31,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T30,T31,T82 Yes T30,T31,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T73,T129,T110 Yes T73,T129,T110 OUTPUT
pwr_ast_i.main_pok Yes Yes T4,T18,T73 Yes T4,T5,T6 INPUT
pwr_ast_i.usb_clk_val Yes Yes T4,T18,T73 Yes T4,T5,T6 INPUT
pwr_ast_i.io_clk_val Yes Yes T4,T18,T73 Yes T4,T5,T6 INPUT
pwr_ast_i.core_clk_val Yes Yes T4,T18,T73 Yes T4,T5,T6 INPUT
pwr_ast_i.slow_clk_val Yes Yes T78,T150,T154 Yes T4,T5,T6 INPUT
pwr_ast_o.usb_clk_en Yes Yes T4,T18,T73 Yes T4,T5,T6 OUTPUT
pwr_ast_o.io_clk_en Yes Yes T4,T18,T73 Yes T4,T5,T6 OUTPUT
pwr_ast_o.core_clk_en Yes Yes T4,T18,T73 Yes T4,T5,T6 OUTPUT
pwr_ast_o.slow_clk_en No No No OUTPUT
pwr_ast_o.pwr_clamp Yes Yes T4,T5,T6 Yes T4,T18,T73 OUTPUT
pwr_ast_o.pwr_clamp_env Yes Yes T4,T5,T6 Yes T4,T18,T73 OUTPUT
pwr_ast_o.main_pd_n Yes Yes T73,T144,T153 Yes T73,T144,T153 OUTPUT
pwr_rst_i.rst_sys_src_n[1:0] Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_rst_i.rst_lc_src_n[1:0] Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_rst_o.reset_cause[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T17 OUTPUT
pwr_rst_o.rstreqs[4:0] Yes Yes T48,T290,T356 Yes T48,T290,T356 OUTPUT
pwr_rst_o.rst_sys_req[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T17 OUTPUT
pwr_rst_o.rst_lc_req[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T17 OUTPUT
pwr_clk_o.usb_ip_clk_en Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
pwr_clk_o.io_ip_clk_en Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
pwr_clk_o.main_ip_clk_en Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
pwr_clk_i.usb_status Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_clk_i.io_status Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_clk_i.main_status Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_otp_i.otp_idle Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_otp_i.otp_done Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_otp_o.otp_init Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
pwr_lc_i.lc_idle Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_lc_i.lc_done Yes Yes T4,T5,T17 Yes T4,T5,T6 INPUT
pwr_lc_o.lc_init Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
pwr_flash_i.flash_idle Yes Yes T58,T129,T261 Yes T58,T129,T261 INPUT
pwr_cpu_i.core_sleeping Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
fetch_en_o[3:0] Yes Yes T4,T5,T17 Yes T4,T5,T6 OUTPUT
lc_hw_debug_en_i[3:0] Yes Yes T5,T17,T18 Yes T5,T6,T17 INPUT
lc_dft_en_i[3:0] Yes Yes T5,T17,T18 Yes T5,T6,T17 INPUT
wakeups_i[5:0] Yes Yes T48,T290,T356 Yes T48,T63,T290 INPUT
rstreqs_i[1:0] Yes Yes T48,T290,T356 Yes T48,T290,T356 INPUT
ndmreset_req_i Yes Yes T8,T9,T19 Yes T8,T9,T19 INPUT
strap_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
low_power_o Yes Yes T4,T5,T6 Yes T4,T18,T73 OUTPUT
rom_ctrl_i.good[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T17 INPUT
rom_ctrl_i.done[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T17 INPUT
sw_rst_req_i[3:0] Yes Yes T58,T129,T133 Yes T58,T129,T133 INPUT
esc_rst_tx_i.esc_n Yes Yes T5,T17,T75 Yes T5,T17,T75 INPUT
esc_rst_tx_i.esc_p Yes Yes T5,T17,T75 Yes T5,T17,T75 INPUT
esc_rst_rx_o.resp_n Yes Yes T5,T17,T75 Yes T5,T17,T75 OUTPUT
esc_rst_rx_o.resp_p Yes Yes T5,T17,T75 Yes T5,T17,T75 OUTPUT
intr_wakeup_o Yes Yes T144,T292,T119 Yes T144,T292,T119 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%