Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T232,T234,T314
0	1	Covered	T232,T234,T314
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T232,T234,T314
1	Covered	T232,T234,T314

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T232,T234,T314
1	Covered	T232,T234,T314

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T232,T234,T314
1	1	Covered	T232,T234,T314

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T232,T234,T314
1	0	Covered	T232,T234,T314
1	1	Covered	T232,T234,T314

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T232,T234,T314

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T232,T234,T314
0	Covered	T232,T234,T314

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T232,T234,T314
0	Covered	T232,T234,T314

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	952270168	936710112	0	0
CheckNGreaterZero_A	1976	1976	0	0
GntImpliesReady_A	952270168	8373	0	0
GntImpliesValid_A	952270168	8373	0	0
GrantKnown_A	952270168	936710112	0	0
IdxKnown_A	952270168	936710112	0	0
IndexIsCorrect_A	952270168	8373	0	0
NoReadyValidNoGrant_A	952270168	0	0	0
Priority_A	952270168	8373	0	0
ReadyAndValidImplyGrant_A	952270168	8373	0	0
ReqAndReadyImplyGrant_A	952270168	8373	0	0
ReqImpliesValid_A	952270168	8373	0	0
ValidKnown_A	952270168	936710112	0	0
gen_data_port_assertion.DataFlow_A	952270168	8373	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	936710112	0	0
T4	101122	100888	0	0
T5	520544	520332	0	0
T6	665318	665208	0	0
T17	464342	464116	0	0
T18	1400612	0	0	0
T32	186002	185892	0	0
T58	1006442	1006092	0	0
T73	324598	324286	0	0
T75	464244	464024	0	0
T83	145364	145240	0	0
T144	0	569774	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1976	1976	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T32	2	2	0	0
T58	2	2	0	0
T73	2	2	0	0
T75	2	2	0	0
T83	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	8373	0	0
T27	560882	0	0	0
T63	362776	0	0	0
T69	273882	0	0	0
T135	515972	0	0	0
T139	148584	0	0	0
T141	207426	0	0	0
T224	1010624	0	0	0
T232	185198	2780	0	0
T234	0	2797	0	0
T289	593366	0	0	0
T314	0	2796	0	0
T317	153556	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	8373	0	0
T27	560882	0	0	0
T63	362776	0	0	0
T69	273882	0	0	0
T135	515972	0	0	0
T139	148584	0	0	0
T141	207426	0	0	0
T224	1010624	0	0	0
T232	185198	2780	0	0
T234	0	2797	0	0
T289	593366	0	0	0
T314	0	2796	0	0
T317	153556	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	936710112	0	0
T4	101122	100888	0	0
T5	520544	520332	0	0
T6	665318	665208	0	0
T17	464342	464116	0	0
T18	1400612	0	0	0
T32	186002	185892	0	0
T58	1006442	1006092	0	0
T73	324598	324286	0	0
T75	464244	464024	0	0
T83	145364	145240	0	0
T144	0	569774	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	936710112	0	0
T4	101122	100888	0	0
T5	520544	520332	0	0
T6	665318	665208	0	0
T17	464342	464116	0	0
T18	1400612	0	0	0
T32	186002	185892	0	0
T58	1006442	1006092	0	0
T73	324598	324286	0	0
T75	464244	464024	0	0
T83	145364	145240	0	0
T144	0	569774	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	8373	0	0
T27	560882	0	0	0
T63	362776	0	0	0
T69	273882	0	0	0
T135	515972	0	0	0
T139	148584	0	0	0
T141	207426	0	0	0
T224	1010624	0	0	0
T232	185198	2780	0	0
T234	0	2797	0	0
T289	593366	0	0	0
T314	0	2796	0	0
T317	153556	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	8373	0	0
T27	560882	0	0	0
T63	362776	0	0	0
T69	273882	0	0	0
T135	515972	0	0	0
T139	148584	0	0	0
T141	207426	0	0	0
T224	1010624	0	0	0
T232	185198	2780	0	0
T234	0	2797	0	0
T289	593366	0	0	0
T314	0	2796	0	0
T317	153556	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	8373	0	0
T27	560882	0	0	0
T63	362776	0	0	0
T69	273882	0	0	0
T135	515972	0	0	0
T139	148584	0	0	0
T141	207426	0	0	0
T224	1010624	0	0	0
T232	185198	2780	0	0
T234	0	2797	0	0
T289	593366	0	0	0
T314	0	2796	0	0
T317	153556	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	8373	0	0
T27	560882	0	0	0
T63	362776	0	0	0
T69	273882	0	0	0
T135	515972	0	0	0
T139	148584	0	0	0
T141	207426	0	0	0
T224	1010624	0	0	0
T232	185198	2780	0	0
T234	0	2797	0	0
T289	593366	0	0	0
T314	0	2796	0	0
T317	153556	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	8373	0	0
T27	560882	0	0	0
T63	362776	0	0	0
T69	273882	0	0	0
T135	515972	0	0	0
T139	148584	0	0	0
T141	207426	0	0	0
T224	1010624	0	0	0
T232	185198	2780	0	0
T234	0	2797	0	0
T289	593366	0	0	0
T314	0	2796	0	0
T317	153556	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	936710112	0	0
T4	101122	100888	0	0
T5	520544	520332	0	0
T6	665318	665208	0	0
T17	464342	464116	0	0
T18	1400612	0	0	0
T32	186002	185892	0	0
T58	1006442	1006092	0	0
T73	324598	324286	0	0
T75	464244	464024	0	0
T83	145364	145240	0	0
T144	0	569774	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952270168	8373	0	0
T27	560882	0	0	0
T63	362776	0	0	0
T69	273882	0	0	0
T135	515972	0	0	0
T139	148584	0	0	0
T141	207426	0	0	0
T224	1010624	0	0	0
T232	185198	2780	0	0
T234	0	2797	0	0
T289	593366	0	0	0
T314	0	2796	0	0
T317	153556	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T232,T234,T314
0	1	Covered	T232,T234,T314
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T232,T234,T314
1	Covered	T232,T234,T314

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T232,T234,T314
1	Covered	T232,T234,T314

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T232,T234,T314
1	1	Covered	T232,T234,T314

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T232,T234,T314
1	0	Covered	T232,T234,T314
1	1	Covered	T232,T234,T314

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T232,T234,T314

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T232,T234,T314
0	Covered	T232,T234,T314

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T232,T234,T314
0	Covered	T232,T234,T314

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	476135084	468355056	0	0
CheckNGreaterZero_A	988	988	0	0
GntImpliesReady_A	476135084	5183	0	0
GntImpliesValid_A	476135084	5183	0	0
GrantKnown_A	476135084	468355056	0	0
IdxKnown_A	476135084	468355056	0	0
IndexIsCorrect_A	476135084	5183	0	0
NoReadyValidNoGrant_A	476135084	0	0	0
Priority_A	476135084	5183	0	0
ReadyAndValidImplyGrant_A	476135084	5183	0	0
ReqAndReadyImplyGrant_A	476135084	5183	0	0
ReqImpliesValid_A	476135084	5183	0	0
ValidKnown_A	476135084	468355056	0	0
gen_data_port_assertion.DataFlow_A	476135084	5183	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	468355056	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	0	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0
T144	0	284887	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5183	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1716	0	0
T234	0	1734	0	0
T289	296683	0	0	0
T314	0	1733	0	0
T317	76778	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5183	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1716	0	0
T234	0	1734	0	0
T289	296683	0	0	0
T314	0	1733	0	0
T317	76778	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	468355056	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	0	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0
T144	0	284887	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	468355056	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	0	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0
T144	0	284887	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5183	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1716	0	0
T234	0	1734	0	0
T289	296683	0	0	0
T314	0	1733	0	0
T317	76778	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5183	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1716	0	0
T234	0	1734	0	0
T289	296683	0	0	0
T314	0	1733	0	0
T317	76778	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5183	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1716	0	0
T234	0	1734	0	0
T289	296683	0	0	0
T314	0	1733	0	0
T317	76778	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5183	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1716	0	0
T234	0	1734	0	0
T289	296683	0	0	0
T314	0	1733	0	0
T317	76778	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5183	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1716	0	0
T234	0	1734	0	0
T289	296683	0	0	0
T314	0	1733	0	0
T317	76778	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	468355056	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	0	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0
T144	0	284887	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	5183	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1716	0	0
T234	0	1734	0	0
T289	296683	0	0	0
T314	0	1733	0	0
T317	76778	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T232,T234,T314
0	1	Covered	T232,T234,T314
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T232,T234,T314
1	Covered	T232,T234,T314

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T232,T234,T314
1	Covered	T232,T234,T314

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T232,T234,T314
1	1	Covered	T232,T234,T314

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T232,T234,T314
1	0	Covered	T232,T234,T314
1	1	Covered	T232,T234,T314

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T232,T234,T314

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T232,T234,T314
0	Covered	T232,T234,T314

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T232,T234,T314
0	Covered	T232,T234,T314

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	476135084	468355056	0	0
CheckNGreaterZero_A	988	988	0	0
GntImpliesReady_A	476135084	3190	0	0
GntImpliesValid_A	476135084	3190	0	0
GrantKnown_A	476135084	468355056	0	0
IdxKnown_A	476135084	468355056	0	0
IndexIsCorrect_A	476135084	3190	0	0
NoReadyValidNoGrant_A	476135084	0	0	0
Priority_A	476135084	3190	0	0
ReadyAndValidImplyGrant_A	476135084	3190	0	0
ReqAndReadyImplyGrant_A	476135084	3190	0	0
ReqImpliesValid_A	476135084	3190	0	0
ValidKnown_A	476135084	468355056	0	0
gen_data_port_assertion.DataFlow_A	476135084	3190	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	468355056	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	0	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0
T144	0	284887	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	988	988	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T32	1	1	0	0
T58	1	1	0	0
T73	1	1	0	0
T75	1	1	0	0
T83	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3190	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1064	0	0
T234	0	1063	0	0
T289	296683	0	0	0
T314	0	1063	0	0
T317	76778	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3190	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1064	0	0
T234	0	1063	0	0
T289	296683	0	0	0
T314	0	1063	0	0
T317	76778	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	468355056	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	0	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0
T144	0	284887	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	468355056	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	0	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0
T144	0	284887	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3190	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1064	0	0
T234	0	1063	0	0
T289	296683	0	0	0
T314	0	1063	0	0
T317	76778	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3190	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1064	0	0
T234	0	1063	0	0
T289	296683	0	0	0
T314	0	1063	0	0
T317	76778	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3190	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1064	0	0
T234	0	1063	0	0
T289	296683	0	0	0
T314	0	1063	0	0
T317	76778	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3190	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1064	0	0
T234	0	1063	0	0
T289	296683	0	0	0
T314	0	1063	0	0
T317	76778	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3190	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1064	0	0
T234	0	1063	0	0
T289	296683	0	0	0
T314	0	1063	0	0
T317	76778	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	468355056	0	0
T4	50561	50444	0	0
T5	260272	260166	0	0
T6	332659	332604	0	0
T17	232171	232058	0	0
T18	700306	0	0	0
T32	93001	92946	0	0
T58	503221	503046	0	0
T73	162299	162143	0	0
T75	232122	232012	0	0
T83	72682	72620	0	0
T144	0	284887	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	476135084	3190	0	0
T27	280441	0	0	0
T63	181388	0	0	0
T69	136941	0	0	0
T135	257986	0	0	0
T139	74292	0	0	0
T141	103713	0	0	0
T224	505312	0	0	0
T232	92599	1064	0	0
T234	0	1063	0	0
T289	296683	0	0	0
T314	0	1063	0	0
T317	76778	0	0	0