Unified Coverage Report :: Module :: chip_earlgrey_asic

Module : chip_earlgrey_asic

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.90	80.00	100.00	95.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	92.83	80.00	100.00	98.48

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.83	80.00	100.00	98.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.76	90.84	80.16	89.65		91.87	81.31

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
top_earlgrey	85.55	90.67	78.56	89.54		91.54	77.45
u_ast	87.36			87.36
u_padring	99.04	99.21	99.81	96.57		99.60	100.00
u_prim_usb_diff_rx	96.30	100.00	88.89			100.00

Line Coverage for Module : chip_earlgrey_asic

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	789	1	0	0.00
CONT_ASSIGN	802	1	0	0.00
CONT_ASSIGN	831	1	0	0.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	861	1	0	0.00
CONT_ASSIGN	864	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1032	1	1	100.00
CONT_ASSIGN	1039	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1058	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00
CONT_ASSIGN	1063	1	1	100.00
CONT_ASSIGN	1064	1	1	100.00
CONT_ASSIGN	1065	1	1	100.00
CONT_ASSIGN	1066	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
214	1	1
215	1	1
789	0	1
802	0	1
831	0	1
839	0	1
846	1	1
849	1	1
855	1	1
857	1	1
861	0	1
864	1	1
1029	1	1
1030	1	1
1031	1	1
1032	1	1
1039	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1
1063	1	1
1064	1	1
1065	1	1
1066	1	1

---

Cond Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T73,T144,T292

---

Toggle Coverage for Module : chip_earlgrey_asic

	Total	Covered	Percent
Totals	70	64	91.43
Total Bits	140	134	95.71
Total Bits 0->1	70	70	100.00
Total Bits 1->0	70	64	91.43

Ports	70	64	91.43
Port Bits	140	134	95.71
Port Bits 0->1	70	70	100.00
Port Bits 1->0	70	64	91.43

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
POR_N	Yes	Yes	T4,T18,T33	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T43,T34,T44	Yes	T43,T44,T45	INOUT
USB_N	Yes	Yes	T43,T44,T45	Yes	T43,T34,T44	INOUT
CC1	No	No		Yes	T34,T35,T36	INOUT
CC2	No	No		Yes	T34,T35,T36	INOUT
FLASH_TEST_VOLT	No	No		Yes	T34,T35,T36	INOUT
FLASH_TEST_MODE0	No	No		Yes	T34,T35,T36	INOUT
FLASH_TEST_MODE1	No	No		Yes	T34,T35,T36	INOUT
OTP_EXT_VOLT	No	No		Yes	T34,T35,T36	INOUT
SPI_HOST_D0	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INOUT
SPI_HOST_D1	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INOUT
SPI_HOST_D2	Yes	Yes	T39,T121,T122	Yes	T39,T121,T35	INOUT
SPI_HOST_D3	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INOUT
SPI_HOST_CLK	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INOUT
SPI_HOST_CS_L	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INOUT
SPI_DEV_D0	Yes	Yes	T37,T66,T149	Yes	T37,T66,T149	INOUT
SPI_DEV_D1	Yes	Yes	T37,T66,T149	Yes	T37,T66,T149	INOUT
SPI_DEV_D2	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INOUT
SPI_DEV_D3	Yes	Yes	T39,T121,T122	Yes	T39,T121,T35	INOUT
SPI_DEV_CLK	Yes	Yes	T37,T66,T149	Yes	T37,T34,T66	INOUT
SPI_DEV_CS_L	Yes	Yes	T37,T34,T149	Yes	T37,T34,T149	INOUT
IOR8	Yes	Yes	T48,T34,T49	Yes	T48,T34,T49	INOUT
IOR9	Yes	Yes	T48,T49,T254	Yes	T48,T63,T34	INOUT
IOA0	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INOUT
IOA1	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INOUT
IOA2	Yes	Yes	T41,T156,T42	Yes	T41,T156,T42	INOUT
IOA3	Yes	Yes	T41,T42,T10	Yes	T34,T41,T42	INOUT
IOA4	Yes	Yes	T173,T174,T175	Yes	T173,T174,T175	INOUT
IOA5	Yes	Yes	T173,T174,T175	Yes	T173,T174,T175	INOUT
IOA6	Yes	Yes	T41,T42,T10	Yes	T41,T42,T10	INOUT
IOA7	Yes	Yes	T66,T41,T42	Yes	T66,T41,T42	INOUT
IOA8	Yes	Yes	T41,T42,T101	Yes	T41,T42,T101	INOUT
IOB0	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INOUT
IOB1	Yes	Yes	T59,T60,T61	Yes	T34,T59,T35	INOUT
IOB2	Yes	Yes	T3,T55,T56	Yes	T3,T55,T56	INOUT
IOB3	Yes	Yes	T48,T49,T254	Yes	T34,T49,T254	INOUT
IOB4	Yes	Yes	T251,T322,T59	Yes	T251,T322,T59	INOUT
IOB5	Yes	Yes	T34,T251,T322	Yes	T251,T322,T367	INOUT
IOB6	Yes	Yes	T48,T49,T254	Yes	T34,T49,T254	INOUT
IOB7	Yes	Yes	T49,T41,T42	Yes	T48,T63,T34	INOUT
IOB8	Yes	Yes	T49,T254,T41	Yes	T49,T254,T41	INOUT
IOB9	Yes	Yes	T6,T48,T317	Yes	T6,T48,T317	INOUT
IOB10	Yes	Yes	T6,T317,T193	Yes	T6,T317,T193	INOUT
IOB11	Yes	Yes	T317,T320,T41	Yes	T317,T320,T41	INOUT
IOB12	Yes	Yes	T317,T320,T41	Yes	T317,T320,T41	INOUT
IOC0	Yes	Yes	T69,T70,T71	Yes	T34,T252,T253	INOUT
IOC1	Yes	Yes	T149,T251,T252	Yes	T34,T252,T253	INOUT
IOC2	Yes	Yes	T149,T251,T252	Yes	T34,T252,T253	INOUT
IOC3	Yes	Yes	T149,T323,T386	Yes	T149,T323,T386	INOUT
IOC4	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INOUT
IOC5	Yes	Yes	T21,T26,T76	Yes	T21,T26,T76	INOUT
IOC6	Yes	Yes	T4,T33,T78	Yes	T4,T33,T78	INOUT
IOC7	Yes	Yes	T49,T254,T50	Yes	T48,T43,T34	INOUT
IOC8	Yes	Yes	T21,T26,T76	Yes	T21,T34,T26	INOUT
IOC9	Yes	Yes	T63,T49,T41	Yes	T48,T63,T34	INOUT
IOC10	Yes	Yes	T320,T41,T156	Yes	T320,T41,T156	INOUT
IOC11	Yes	Yes	T320,T41,T156	Yes	T320,T41,T156	INOUT
IOC12	Yes	Yes	T320,T41,T156	Yes	T320,T41,T156	INOUT
IOR0	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR1	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR2	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR3	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR4	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR5	Yes	Yes	T48,T49,T41	Yes	T48,T49,T41	INOUT
IOR6	Yes	Yes	T49,T41,T42	Yes	T48,T49,T41	INOUT
IOR7	Yes	Yes	T41,T42,T52	Yes	T34,T41,T42	INOUT
IOR10	Yes	Yes	T41,T42,T52	Yes	T41,T42,T52	INOUT
IOR11	Yes	Yes	T41,T42,T52	Yes	T41,T42,T52	INOUT
IOR12	Yes	Yes	T41,T42,T52	Yes	T34,T41,T42	INOUT
IOR13	Yes	Yes	T254,T41,T42	Yes	T34,T49,T254	INOUT

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		25	20	80.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	215	1	1	100.00
CONT_ASSIGN	789	1	0	0.00
CONT_ASSIGN	802	1	0	0.00
CONT_ASSIGN	831	1	0	0.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	861	1	0	0.00
CONT_ASSIGN	864	1	1	100.00
CONT_ASSIGN	1029	1	1	100.00
CONT_ASSIGN	1030	1	1	100.00
CONT_ASSIGN	1031	1	1	100.00
CONT_ASSIGN	1032	1	1	100.00
CONT_ASSIGN	1039	1	1	100.00
CONT_ASSIGN	1056	1	1	100.00
CONT_ASSIGN	1057	1	1	100.00
CONT_ASSIGN	1058	1	1	100.00
CONT_ASSIGN	1059	1	1	100.00
CONT_ASSIGN	1063	1	1	100.00
CONT_ASSIGN	1064	1	1	100.00
CONT_ASSIGN	1065	1	1	100.00
CONT_ASSIGN	1066	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' or '../src/lowrisc_systems_chip_earlgrey_asic_0.1/rtl/autogen/chip_earlgrey_asic.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
214	1	1
215	1	1
789	0	1
802	0	1
831	0	1
839	0	1
846	1	1
849	1	1
855	1	1
857	1	1
861	0	1
864	1	1
1029	1	1
1030	1	1
1031	1	1
1032	1	1
1039	1	1
1056	1	1
1057	1	1
1058	1	1
1059	1	1
1063	1	1
1064	1	1
1065	1	1
1066	1	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       79
 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
            -----------------------------------1-----------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T73,T144,T292

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	66	64	96.97
Total Bits	132	130	98.48
Total Bits 0->1	66	66	100.00
Total Bits 1->0	66	64	96.97

Ports	66	64	96.97
Port Bits	132	130	98.48
Port Bits 0->1	66	66	100.00
Port Bits 1->0	66	64	96.97

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
POR_N	Yes	Yes	T4,T18,T33	Yes	T4,T5,T6	INOUT
USB_P	Yes	Yes	T43,T34,T44	Yes	T43,T44,T45	INOUT
USB_N	Yes	Yes	T43,T44,T45	Yes	T43,T34,T44	INOUT
CC1	No	No		Yes	T34,T35,T36	INOUT
CC2	No	No		Yes	T34,T35,T36	INOUT
FLASH_TEST_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE0[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
FLASH_TEST_MODE1[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
OTP_EXT_VOLT[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
SPI_HOST_D0	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INOUT
SPI_HOST_D1	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INOUT
SPI_HOST_D2	Yes	Yes	T39,T121,T122	Yes	T39,T121,T35	INOUT
SPI_HOST_D3	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INOUT
SPI_HOST_CLK	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INOUT
SPI_HOST_CS_L	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INOUT
SPI_DEV_D0	Yes	Yes	T37,T66,T149	Yes	T37,T66,T149	INOUT
SPI_DEV_D1	Yes	Yes	T37,T66,T149	Yes	T37,T66,T149	INOUT
SPI_DEV_D2	Yes	Yes	T39,T121,T122	Yes	T39,T121,T122	INOUT
SPI_DEV_D3	Yes	Yes	T39,T121,T122	Yes	T39,T121,T35	INOUT
SPI_DEV_CLK	Yes	Yes	T37,T66,T149	Yes	T37,T34,T66	INOUT
SPI_DEV_CS_L	Yes	Yes	T37,T34,T149	Yes	T37,T34,T149	INOUT
IOR8	Yes	Yes	T48,T34,T49	Yes	T48,T34,T49	INOUT
IOR9	Yes	Yes	T48,T49,T254	Yes	T48,T63,T34	INOUT
IOA0	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INOUT
IOA1	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	INOUT
IOA2	Yes	Yes	T41,T156,T42	Yes	T41,T156,T42	INOUT
IOA3	Yes	Yes	T41,T42,T10	Yes	T34,T41,T42	INOUT
IOA4	Yes	Yes	T173,T174,T175	Yes	T173,T174,T175	INOUT
IOA5	Yes	Yes	T173,T174,T175	Yes	T173,T174,T175	INOUT
IOA6	Yes	Yes	T41,T42,T10	Yes	T41,T42,T10	INOUT
IOA7	Yes	Yes	T66,T41,T42	Yes	T66,T41,T42	INOUT
IOA8	Yes	Yes	T41,T42,T101	Yes	T41,T42,T101	INOUT
IOB0	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	INOUT
IOB1	Yes	Yes	T59,T60,T61	Yes	T34,T59,T35	INOUT
IOB2	Yes	Yes	T3,T55,T56	Yes	T3,T55,T56	INOUT
IOB3	Yes	Yes	T48,T49,T254	Yes	T34,T49,T254	INOUT
IOB4	Yes	Yes	T251,T322,T59	Yes	T251,T322,T59	INOUT
IOB5	Yes	Yes	T34,T251,T322	Yes	T251,T322,T367	INOUT
IOB6	Yes	Yes	T48,T49,T254	Yes	T34,T49,T254	INOUT
IOB7	Yes	Yes	T49,T41,T42	Yes	T48,T63,T34	INOUT
IOB8	Yes	Yes	T49,T254,T41	Yes	T49,T254,T41	INOUT
IOB9	Yes	Yes	T6,T48,T317	Yes	T6,T48,T317	INOUT
IOB10	Yes	Yes	T6,T317,T193	Yes	T6,T317,T193	INOUT
IOB11	Yes	Yes	T317,T320,T41	Yes	T317,T320,T41	INOUT
IOB12	Yes	Yes	T317,T320,T41	Yes	T317,T320,T41	INOUT
IOC0	Yes	Yes	T69,T70,T71	Yes	T34,T252,T253	INOUT
IOC1	Yes	Yes	T149,T251,T252	Yes	T34,T252,T253	INOUT
IOC2	Yes	Yes	T149,T251,T252	Yes	T34,T252,T253	INOUT
IOC3	Yes	Yes	T149,T323,T386	Yes	T149,T323,T386	INOUT
IOC4	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	INOUT
IOC5	Yes	Yes	T21,T26,T76	Yes	T21,T26,T76	INOUT
IOC6	Yes	Yes	T4,T33,T78	Yes	T4,T33,T78	INOUT
IOC7	Yes	Yes	T49,T254,T50	Yes	T48,T43,T34	INOUT
IOC8	Yes	Yes	T21,T26,T76	Yes	T21,T34,T26	INOUT
IOC9	Yes	Yes	T63,T49,T41	Yes	T48,T63,T34	INOUT
IOC10	Yes	Yes	T320,T41,T156	Yes	T320,T41,T156	INOUT
IOC11	Yes	Yes	T320,T41,T156	Yes	T320,T41,T156	INOUT
IOC12	Yes	Yes	T320,T41,T156	Yes	T320,T41,T156	INOUT
IOR0	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR1	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR2	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR3	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR4	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INOUT
IOR5	Yes	Yes	T48,T49,T41	Yes	T48,T49,T41	INOUT
IOR6	Yes	Yes	T49,T41,T42	Yes	T48,T49,T41	INOUT
IOR7	Yes	Yes	T41,T42,T52	Yes	T34,T41,T42	INOUT
IOR10	Yes	Yes	T41,T42,T52	Yes	T41,T42,T52	INOUT
IOR11	Yes	Yes	T41,T42,T52	Yes	T41,T42,T52	INOUT
IOR12	Yes	Yes	T41,T42,T52	Yes	T34,T41,T42	INOUT
IOR13	Yes	Yes	T254,T41,T42	Yes	T34,T49,T254	INOUT