Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.45 90.84 80.16 89.65 91.87 81.31 84.87


Total test records in report: 988
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T100 /workspace/coverage/default/2.chip_sw_edn_boot_mode.194552801 Jun 22 07:38:24 PM PDT 24 Jun 22 07:47:46 PM PDT 24 3160855040 ps
T101 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3728874787 Jun 22 07:32:00 PM PDT 24 Jun 22 07:43:27 PM PDT 24 3878984574 ps
T102 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.308371860 Jun 22 07:17:54 PM PDT 24 Jun 22 07:24:46 PM PDT 24 8106395834 ps
T103 /workspace/coverage/default/25.chip_sw_all_escalation_resets.2723275003 Jun 22 07:42:34 PM PDT 24 Jun 22 07:50:43 PM PDT 24 4227838750 ps
T104 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1136093163 Jun 22 07:11:28 PM PDT 24 Jun 22 07:26:08 PM PDT 24 8466437900 ps
T105 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2259875728 Jun 22 07:40:52 PM PDT 24 Jun 22 07:48:51 PM PDT 24 3870366674 ps
T196 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.977682173 Jun 22 07:48:34 PM PDT 24 Jun 22 07:55:01 PM PDT 24 4110092852 ps
T568 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2064945055 Jun 22 07:32:36 PM PDT 24 Jun 22 08:38:57 PM PDT 24 15941778456 ps
T142 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4179447607 Jun 22 07:11:30 PM PDT 24 Jun 22 07:20:49 PM PDT 24 6108045336 ps
T569 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.232594955 Jun 22 07:27:13 PM PDT 24 Jun 22 07:30:46 PM PDT 24 2520895620 ps
T532 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1768445401 Jun 22 07:38:01 PM PDT 24 Jun 22 07:48:10 PM PDT 24 4819036100 ps
T570 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.705997745 Jun 22 07:27:12 PM PDT 24 Jun 22 07:30:48 PM PDT 24 2347719760 ps
T288 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2745925119 Jun 22 07:16:43 PM PDT 24 Jun 22 07:22:43 PM PDT 24 2917973204 ps
T571 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2504911990 Jun 22 07:34:08 PM PDT 24 Jun 22 07:48:38 PM PDT 24 5220340916 ps
T185 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1261753067 Jun 22 07:47:52 PM PDT 24 Jun 22 07:54:53 PM PDT 24 3789417832 ps
T327 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1713285508 Jun 22 07:42:19 PM PDT 24 Jun 22 07:49:02 PM PDT 24 3724124546 ps
T334 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1392578089 Jun 22 07:42:29 PM PDT 24 Jun 22 07:48:54 PM PDT 24 4161637352 ps
T303 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1066438931 Jun 22 07:21:38 PM PDT 24 Jun 22 07:30:09 PM PDT 24 5093052910 ps
T391 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.858719680 Jun 22 07:20:20 PM PDT 24 Jun 22 07:25:58 PM PDT 24 3899677180 ps
T178 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2977703464 Jun 22 07:20:36 PM PDT 24 Jun 22 07:52:51 PM PDT 24 7523318504 ps
T572 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.374191275 Jun 22 07:34:08 PM PDT 24 Jun 22 07:41:43 PM PDT 24 4364001800 ps
T573 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3419448987 Jun 22 07:29:35 PM PDT 24 Jun 22 07:43:36 PM PDT 24 9402432492 ps
T206 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2022064065 Jun 22 07:15:43 PM PDT 24 Jun 22 07:36:26 PM PDT 24 6341627122 ps
T574 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.211540589 Jun 22 07:34:29 PM PDT 24 Jun 22 07:39:38 PM PDT 24 3403129260 ps
T304 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.283975564 Jun 22 07:28:10 PM PDT 24 Jun 22 07:39:51 PM PDT 24 4716271000 ps
T28 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2577316074 Jun 22 07:36:11 PM PDT 24 Jun 22 11:13:01 PM PDT 24 255863893896 ps
T575 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2833136716 Jun 22 07:38:32 PM PDT 24 Jun 22 07:43:37 PM PDT 24 2840658448 ps
T576 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3291215686 Jun 22 07:12:00 PM PDT 24 Jun 22 07:22:32 PM PDT 24 5884908415 ps
T158 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2163732744 Jun 22 07:13:45 PM PDT 24 Jun 22 07:28:09 PM PDT 24 18503641320 ps
T577 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2143412978 Jun 22 07:34:28 PM PDT 24 Jun 22 07:49:24 PM PDT 24 13179469256 ps
T265 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2923990669 Jun 22 07:13:03 PM PDT 24 Jun 22 07:52:25 PM PDT 24 20129934188 ps
T487 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.154732511 Jun 22 07:47:26 PM PDT 24 Jun 22 07:53:28 PM PDT 24 3799412580 ps
T578 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3271887176 Jun 22 07:38:06 PM PDT 24 Jun 22 07:47:44 PM PDT 24 3423802758 ps
T579 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2538325067 Jun 22 07:36:31 PM PDT 24 Jun 22 07:48:43 PM PDT 24 4160338180 ps
T580 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.151095483 Jun 22 07:37:14 PM PDT 24 Jun 22 07:41:46 PM PDT 24 2994731296 ps
T581 /workspace/coverage/default/4.chip_tap_straps_prod.1380556722 Jun 22 07:39:41 PM PDT 24 Jun 22 08:02:16 PM PDT 24 13392616712 ps
T207 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.77522811 Jun 22 07:18:47 PM PDT 24 Jun 22 08:23:06 PM PDT 24 17058076080 ps
T582 /workspace/coverage/default/0.chip_sw_uart_tx_rx.435872257 Jun 22 07:12:48 PM PDT 24 Jun 22 07:23:53 PM PDT 24 3977512750 ps
T255 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2898815206 Jun 22 07:12:36 PM PDT 24 Jun 22 07:22:29 PM PDT 24 4625061077 ps
T114 /workspace/coverage/default/71.chip_sw_all_escalation_resets.328225621 Jun 22 07:46:18 PM PDT 24 Jun 22 07:58:35 PM PDT 24 4657751098 ps
T115 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1732044071 Jun 22 07:13:54 PM PDT 24 Jun 22 07:20:08 PM PDT 24 3244987740 ps
T198 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1264171356 Jun 22 07:16:19 PM PDT 24 Jun 22 07:26:55 PM PDT 24 4362088200 ps
T369 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2400627196 Jun 22 07:39:30 PM PDT 24 Jun 22 07:59:13 PM PDT 24 8609921331 ps
T237 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1399582106 Jun 22 07:32:54 PM PDT 24 Jun 22 07:41:16 PM PDT 24 3850090472 ps
T420 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1117656404 Jun 22 07:20:21 PM PDT 24 Jun 22 07:42:14 PM PDT 24 7239495096 ps
T29 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3630342660 Jun 22 07:45:23 PM PDT 24 Jun 22 07:55:19 PM PDT 24 5305823942 ps
T583 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1007695291 Jun 22 07:28:57 PM PDT 24 Jun 22 07:41:06 PM PDT 24 4139057176 ps
T529 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.921328139 Jun 22 07:42:34 PM PDT 24 Jun 22 07:49:57 PM PDT 24 3520676680 ps
T584 /workspace/coverage/default/0.rom_e2e_static_critical.4119033125 Jun 22 07:18:31 PM PDT 24 Jun 22 08:31:34 PM PDT 24 16792325816 ps
T585 /workspace/coverage/default/2.rom_e2e_asm_init_prod.886270572 Jun 22 07:40:00 PM PDT 24 Jun 22 08:37:42 PM PDT 24 16265396263 ps
T586 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3625178145 Jun 22 07:30:03 PM PDT 24 Jun 22 07:38:15 PM PDT 24 4826652118 ps
T587 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2061373580 Jun 22 07:33:15 PM PDT 24 Jun 22 07:53:56 PM PDT 24 11934196693 ps
T282 /workspace/coverage/default/33.chip_sw_all_escalation_resets.313847276 Jun 22 07:44:22 PM PDT 24 Jun 22 07:54:28 PM PDT 24 6225423628 ps
T588 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1516684594 Jun 22 07:32:55 PM PDT 24 Jun 22 08:05:17 PM PDT 24 31570772606 ps
T589 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3991340355 Jun 22 07:32:02 PM PDT 24 Jun 22 08:05:43 PM PDT 24 9795971152 ps
T534 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1531569124 Jun 22 07:47:11 PM PDT 24 Jun 22 07:59:20 PM PDT 24 5381454352 ps
T530 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3662872696 Jun 22 07:50:58 PM PDT 24 Jun 22 07:56:31 PM PDT 24 4119723000 ps
T162 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3505953317 Jun 22 07:36:46 PM PDT 24 Jun 22 08:47:44 PM PDT 24 26617699169 ps
T590 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3072818760 Jun 22 07:30:40 PM PDT 24 Jun 22 07:34:52 PM PDT 24 3111768301 ps
T418 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444842124 Jun 22 07:45:09 PM PDT 24 Jun 22 07:52:59 PM PDT 24 3561196258 ps
T330 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3629157905 Jun 22 07:13:39 PM PDT 24 Jun 22 07:23:05 PM PDT 24 5762111960 ps
T300 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3531883506 Jun 22 07:30:22 PM PDT 24 Jun 22 07:32:08 PM PDT 24 2646288687 ps
T181 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3639255779 Jun 22 07:46:42 PM PDT 24 Jun 22 07:56:59 PM PDT 24 4751626840 ps
T67 /workspace/coverage/default/1.chip_sw_spi_device_tpm.2538061375 Jun 22 07:18:11 PM PDT 24 Jun 22 07:24:08 PM PDT 24 2676904196 ps
T591 /workspace/coverage/default/2.rom_keymgr_functest.2541023417 Jun 22 07:37:02 PM PDT 24 Jun 22 07:44:19 PM PDT 24 3775157520 ps
T229 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3724068554 Jun 22 07:15:47 PM PDT 24 Jun 22 07:18:20 PM PDT 24 3297450107 ps
T46 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1480340270 Jun 22 07:11:50 PM PDT 24 Jun 22 07:20:44 PM PDT 24 4089747688 ps
T485 /workspace/coverage/default/95.chip_sw_all_escalation_resets.3640708934 Jun 22 07:48:16 PM PDT 24 Jun 22 07:59:34 PM PDT 24 5863180596 ps
T592 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3982996637 Jun 22 07:18:39 PM PDT 24 Jun 22 08:40:31 PM PDT 24 16074509032 ps
T417 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1442473845 Jun 22 07:12:37 PM PDT 24 Jun 22 07:21:14 PM PDT 24 3569443242 ps
T505 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3282175589 Jun 22 07:42:18 PM PDT 24 Jun 22 07:50:09 PM PDT 24 3876932180 ps
T147 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3973220454 Jun 22 07:22:52 PM PDT 24 Jun 22 07:38:23 PM PDT 24 9700065607 ps
T419 /workspace/coverage/default/63.chip_sw_all_escalation_resets.680945539 Jun 22 07:47:24 PM PDT 24 Jun 22 07:57:21 PM PDT 24 5270418736 ps
T199 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3403561514 Jun 22 07:15:18 PM PDT 24 Jun 22 07:28:30 PM PDT 24 5109548522 ps
T305 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2653396728 Jun 22 07:35:51 PM PDT 24 Jun 22 07:45:55 PM PDT 24 5408513521 ps
T168 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1750785938 Jun 22 07:33:31 PM PDT 24 Jun 22 07:40:59 PM PDT 24 5476286656 ps
T80 /workspace/coverage/default/0.chip_tap_straps_rma.1492843045 Jun 22 07:09:14 PM PDT 24 Jun 22 07:16:54 PM PDT 24 5404176403 ps
T171 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1589471591 Jun 22 07:13:08 PM PDT 24 Jun 22 07:32:34 PM PDT 24 7592048032 ps
T593 /workspace/coverage/default/2.chip_sw_hmac_multistream.3937474028 Jun 22 07:35:22 PM PDT 24 Jun 22 07:56:41 PM PDT 24 6731705128 ps
T594 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3011804500 Jun 22 07:24:47 PM PDT 24 Jun 22 07:31:47 PM PDT 24 2892227208 ps
T421 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.84904707 Jun 22 07:17:25 PM PDT 24 Jun 22 07:33:29 PM PDT 24 6379157023 ps
T2 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1011830256 Jun 22 07:28:23 PM PDT 24 Jun 22 07:32:05 PM PDT 24 2449123320 ps
T445 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1314790875 Jun 22 07:26:43 PM PDT 24 Jun 22 07:44:44 PM PDT 24 5006083320 ps
T446 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.1741269789 Jun 22 07:13:26 PM PDT 24 Jun 22 07:18:13 PM PDT 24 3197332796 ps
T447 /workspace/coverage/default/0.chip_sw_aes_enc.130223505 Jun 22 07:10:29 PM PDT 24 Jun 22 07:15:19 PM PDT 24 3320348650 ps
T234 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.722537296 Jun 22 07:13:01 PM PDT 24 Jun 22 07:18:46 PM PDT 24 2738053820 ps
T59 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.908738970 Jun 22 07:14:51 PM PDT 24 Jun 22 07:19:49 PM PDT 24 2760246928 ps
T448 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3767006388 Jun 22 07:17:49 PM PDT 24 Jun 22 07:19:33 PM PDT 24 2402554662 ps
T395 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1611831928 Jun 22 07:18:04 PM PDT 24 Jun 22 08:01:01 PM PDT 24 35484646300 ps
T319 /workspace/coverage/default/1.chip_sw_power_idle_load.1473842995 Jun 22 07:26:00 PM PDT 24 Jun 22 07:37:53 PM PDT 24 4116029876 ps
T449 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.359508047 Jun 22 07:31:26 PM PDT 24 Jun 22 07:38:25 PM PDT 24 6041476504 ps
T214 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2672904268 Jun 22 07:30:47 PM PDT 24 Jun 22 07:32:46 PM PDT 24 2099236337 ps
T595 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1857330271 Jun 22 07:12:24 PM PDT 24 Jun 22 07:26:55 PM PDT 24 8164820261 ps
T3 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3722002482 Jun 22 07:13:33 PM PDT 24 Jun 22 07:22:52 PM PDT 24 5997901816 ps
T438 /workspace/coverage/default/0.chip_sw_aes_idle.43449602 Jun 22 07:11:39 PM PDT 24 Jun 22 07:16:47 PM PDT 24 2881587806 ps
T439 /workspace/coverage/default/0.chip_sw_power_idle_load.3987759037 Jun 22 07:13:53 PM PDT 24 Jun 22 07:29:21 PM PDT 24 3836351644 ps
T186 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2590527515 Jun 22 07:17:18 PM PDT 24 Jun 22 07:46:34 PM PDT 24 7075449700 ps
T440 /workspace/coverage/default/29.chip_sw_all_escalation_resets.4067628462 Jun 22 07:45:46 PM PDT 24 Jun 22 07:56:02 PM PDT 24 5131584360 ps
T441 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.744102269 Jun 22 07:40:28 PM PDT 24 Jun 22 07:48:21 PM PDT 24 4974623409 ps
T116 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.748061295 Jun 22 07:33:48 PM PDT 24 Jun 22 07:43:17 PM PDT 24 8742677612 ps
T442 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3203298897 Jun 22 07:51:07 PM PDT 24 Jun 22 07:59:10 PM PDT 24 6337449356 ps
T443 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1486754860 Jun 22 07:19:36 PM PDT 24 Jun 22 08:22:48 PM PDT 24 15647153252 ps
T444 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3676797997 Jun 22 07:15:37 PM PDT 24 Jun 22 07:20:00 PM PDT 24 2782663287 ps
T367 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3931679260 Jun 22 07:16:50 PM PDT 24 Jun 22 07:28:03 PM PDT 24 4671714456 ps
T396 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2141298780 Jun 22 07:29:41 PM PDT 24 Jun 22 07:38:46 PM PDT 24 5949000002 ps
T463 /workspace/coverage/default/45.chip_sw_all_escalation_resets.676749291 Jun 22 07:43:39 PM PDT 24 Jun 22 07:55:21 PM PDT 24 5145685582 ps
T596 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.395428735 Jun 22 07:40:00 PM PDT 24 Jun 22 07:48:39 PM PDT 24 5819248764 ps
T597 /workspace/coverage/default/1.chip_tap_straps_testunlock0.486288532 Jun 22 07:25:11 PM PDT 24 Jun 22 07:29:50 PM PDT 24 4116053050 ps
T598 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1799211188 Jun 22 07:17:14 PM PDT 24 Jun 22 07:34:22 PM PDT 24 5598129952 ps
T528 /workspace/coverage/default/19.chip_sw_all_escalation_resets.3135032895 Jun 22 07:41:52 PM PDT 24 Jun 22 07:51:06 PM PDT 24 5366124360 ps
T256 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1021187659 Jun 22 07:19:27 PM PDT 24 Jun 22 07:26:17 PM PDT 24 3529292064 ps
T599 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.4111460798 Jun 22 07:11:55 PM PDT 24 Jun 22 07:21:48 PM PDT 24 4558873726 ps
T454 /workspace/coverage/default/0.chip_tap_straps_dev.2779916233 Jun 22 07:11:04 PM PDT 24 Jun 22 07:31:30 PM PDT 24 13376684159 ps
T600 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3704257977 Jun 22 07:10:42 PM PDT 24 Jun 22 07:22:02 PM PDT 24 4672790744 ps
T462 /workspace/coverage/default/52.chip_sw_all_escalation_resets.2505487777 Jun 22 07:46:01 PM PDT 24 Jun 22 07:56:13 PM PDT 24 5986298316 ps
T151 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.641893387 Jun 22 07:17:22 PM PDT 24 Jun 22 07:24:23 PM PDT 24 7186132375 ps
T152 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3920596358 Jun 22 07:33:14 PM PDT 24 Jun 22 07:38:59 PM PDT 24 3323721290 ps
T601 /workspace/coverage/default/54.chip_sw_all_escalation_resets.3956618187 Jun 22 07:46:43 PM PDT 24 Jun 22 07:58:08 PM PDT 24 6415569344 ps
T373 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3984479158 Jun 22 07:31:33 PM PDT 24 Jun 22 07:49:26 PM PDT 24 5440016610 ps
T602 /workspace/coverage/default/2.chip_sw_csrng_smoketest.1895743323 Jun 22 07:39:56 PM PDT 24 Jun 22 07:43:38 PM PDT 24 3077226570 ps
T30 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2461108602 Jun 22 07:14:45 PM PDT 24 Jun 22 07:42:10 PM PDT 24 11696392336 ps
T314 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3042676272 Jun 22 07:37:22 PM PDT 24 Jun 22 07:43:33 PM PDT 24 3341646304 ps
T603 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2215505696 Jun 22 07:12:01 PM PDT 24 Jun 22 07:23:49 PM PDT 24 4862982816 ps
T111 /workspace/coverage/default/1.chip_sw_alert_test.2074376137 Jun 22 07:19:51 PM PDT 24 Jun 22 07:26:44 PM PDT 24 3534611816 ps
T604 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1268751874 Jun 22 07:26:09 PM PDT 24 Jun 22 07:40:56 PM PDT 24 7288707768 ps
T375 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2356553331 Jun 22 07:29:58 PM PDT 24 Jun 22 07:57:17 PM PDT 24 11257424229 ps
T468 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2398000886 Jun 22 07:44:45 PM PDT 24 Jun 22 07:54:18 PM PDT 24 5347983820 ps
T605 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.672785353 Jun 22 07:21:15 PM PDT 24 Jun 22 07:24:49 PM PDT 24 2704514130 ps
T203 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2922746190 Jun 22 07:12:32 PM PDT 24 Jun 22 07:27:39 PM PDT 24 4645710200 ps
T306 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3699270660 Jun 22 07:10:50 PM PDT 24 Jun 22 07:18:49 PM PDT 24 4623325360 ps
T525 /workspace/coverage/default/86.chip_sw_all_escalation_resets.2123242072 Jun 22 07:47:50 PM PDT 24 Jun 22 07:58:05 PM PDT 24 5279150394 ps
T493 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3136132461 Jun 22 07:44:44 PM PDT 24 Jun 22 07:55:45 PM PDT 24 5143991184 ps
T38 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.4245569445 Jun 22 07:13:53 PM PDT 24 Jun 22 07:26:14 PM PDT 24 6501435154 ps
T606 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3180770802 Jun 22 07:47:53 PM PDT 24 Jun 22 07:56:55 PM PDT 24 5977185104 ps
T329 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4048997933 Jun 22 07:25:44 PM PDT 24 Jun 22 07:33:22 PM PDT 24 4822243485 ps
T169 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3120827919 Jun 22 07:17:19 PM PDT 24 Jun 22 07:24:46 PM PDT 24 5104052736 ps
T39 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2283202177 Jun 22 07:12:54 PM PDT 24 Jun 22 07:23:04 PM PDT 24 4547457380 ps
T47 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3269301461 Jun 22 07:38:29 PM PDT 24 Jun 22 07:45:55 PM PDT 24 5599540852 ps
T607 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2458101967 Jun 22 07:34:10 PM PDT 24 Jun 22 07:44:45 PM PDT 24 4619845972 ps
T387 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.219815804 Jun 22 07:24:42 PM PDT 24 Jun 22 07:28:55 PM PDT 24 3203108359 ps
T608 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2591888830 Jun 22 07:13:39 PM PDT 24 Jun 22 08:52:45 PM PDT 24 24463921848 ps
T609 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.613668154 Jun 22 07:40:55 PM PDT 24 Jun 22 07:50:52 PM PDT 24 4911993150 ps
T354 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.747861014 Jun 22 07:23:18 PM PDT 24 Jun 22 07:46:57 PM PDT 24 11331883160 ps
T610 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.477637249 Jun 22 07:30:16 PM PDT 24 Jun 22 08:37:08 PM PDT 24 47428322100 ps
T366 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2904764021 Jun 22 07:32:35 PM PDT 24 Jun 22 07:39:15 PM PDT 24 3182292248 ps
T286 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2944980044 Jun 22 07:33:36 PM PDT 24 Jun 22 07:37:38 PM PDT 24 3034316732 ps
T611 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3057584227 Jun 22 07:24:11 PM PDT 24 Jun 22 07:35:25 PM PDT 24 4822616952 ps
T612 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2865184775 Jun 22 07:44:50 PM PDT 24 Jun 22 08:39:19 PM PDT 24 16075321496 ps
T613 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.447246573 Jun 22 07:41:47 PM PDT 24 Jun 22 07:51:31 PM PDT 24 4481775454 ps
T336 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3877858713 Jun 22 07:12:33 PM PDT 24 Jun 22 07:41:35 PM PDT 24 11184004935 ps
T614 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3100605275 Jun 22 07:11:32 PM PDT 24 Jun 22 07:15:38 PM PDT 24 3079866940 ps
T615 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.4019088437 Jun 22 07:38:29 PM PDT 24 Jun 22 07:42:43 PM PDT 24 2879194780 ps
T335 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2447502994 Jun 22 07:31:15 PM PDT 24 Jun 22 07:42:59 PM PDT 24 4887635224 ps
T616 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3079929489 Jun 22 07:16:05 PM PDT 24 Jun 22 07:21:14 PM PDT 24 2959841852 ps
T212 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3439549891 Jun 22 07:11:36 PM PDT 24 Jun 22 07:13:13 PM PDT 24 2150977153 ps
T617 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3423336143 Jun 22 07:16:17 PM PDT 24 Jun 22 07:36:49 PM PDT 24 15589314474 ps
T618 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.973964940 Jun 22 07:42:58 PM PDT 24 Jun 22 07:50:02 PM PDT 24 3164502616 ps
T383 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.148978192 Jun 22 07:30:01 PM PDT 24 Jun 22 07:40:27 PM PDT 24 4173938956 ps
T619 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1344409822 Jun 22 07:48:03 PM PDT 24 Jun 22 07:55:12 PM PDT 24 3612668176 ps
T283 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1005356202 Jun 22 07:19:03 PM PDT 24 Jun 22 08:59:21 PM PDT 24 24051483872 ps
T194 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.477953397 Jun 22 07:33:21 PM PDT 24 Jun 22 07:58:50 PM PDT 24 11235008446 ps
T620 /workspace/coverage/default/2.chip_sw_uart_smoketest.24796798 Jun 22 07:40:07 PM PDT 24 Jun 22 07:46:36 PM PDT 24 3578603920 ps
T208 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3000304512 Jun 22 07:12:47 PM PDT 24 Jun 22 08:26:37 PM PDT 24 18609643730 ps
T476 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3409061347 Jun 22 07:40:22 PM PDT 24 Jun 22 07:47:45 PM PDT 24 4165312000 ps
T500 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3110552138 Jun 22 07:46:09 PM PDT 24 Jun 22 07:57:22 PM PDT 24 5267204242 ps
T385 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2595058910 Jun 22 07:13:15 PM PDT 24 Jun 22 07:24:16 PM PDT 24 4349388215 ps
T9 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1685969540 Jun 22 07:15:24 PM PDT 24 Jun 22 07:20:01 PM PDT 24 3898158856 ps
T422 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1294972288 Jun 22 07:11:54 PM PDT 24 Jun 22 07:35:37 PM PDT 24 6666795288 ps
T621 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.573851379 Jun 22 07:29:57 PM PDT 24 Jun 22 07:36:56 PM PDT 24 3371278660 ps
T622 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2943175343 Jun 22 07:20:28 PM PDT 24 Jun 22 07:23:45 PM PDT 24 2455823056 ps
T623 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1285544012 Jun 22 07:19:02 PM PDT 24 Jun 22 07:22:21 PM PDT 24 2565055808 ps
T624 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.894592995 Jun 22 07:16:31 PM PDT 24 Jun 22 07:57:07 PM PDT 24 25354737140 ps
T625 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4202468659 Jun 22 07:11:27 PM PDT 24 Jun 22 07:21:42 PM PDT 24 4966813360 ps
T200 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2319703256 Jun 22 07:13:17 PM PDT 24 Jun 22 07:25:53 PM PDT 24 4587297704 ps
T19 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.373391966 Jun 22 07:35:21 PM PDT 24 Jun 22 07:42:58 PM PDT 24 3448411336 ps
T626 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2614866148 Jun 22 07:40:06 PM PDT 24 Jun 22 07:53:32 PM PDT 24 4602202744 ps
T627 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1947741736 Jun 22 07:38:32 PM PDT 24 Jun 22 07:49:33 PM PDT 24 4534386532 ps
T257 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1894208616 Jun 22 07:22:51 PM PDT 24 Jun 22 07:27:13 PM PDT 24 3530625174 ps
T301 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4213339885 Jun 22 07:11:04 PM PDT 24 Jun 22 07:13:13 PM PDT 24 3235097475 ps
T628 /workspace/coverage/default/1.chip_sw_hmac_multistream.112548441 Jun 22 07:22:12 PM PDT 24 Jun 22 07:47:39 PM PDT 24 7066923744 ps
T204 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2585527341 Jun 22 07:28:43 PM PDT 24 Jun 22 07:44:46 PM PDT 24 5514097712 ps
T629 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2343738387 Jun 22 07:27:43 PM PDT 24 Jun 22 07:31:39 PM PDT 24 2866517592 ps
T630 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1958631522 Jun 22 07:19:47 PM PDT 24 Jun 22 08:30:29 PM PDT 24 16459912648 ps
T631 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.4202826978 Jun 22 07:16:58 PM PDT 24 Jun 22 07:26:49 PM PDT 24 3648918890 ps
T632 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2820400535 Jun 22 07:11:42 PM PDT 24 Jun 22 07:24:07 PM PDT 24 8275065930 ps
T633 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3865698308 Jun 22 07:38:38 PM PDT 24 Jun 22 07:52:13 PM PDT 24 4914517156 ps
T378 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.334751250 Jun 22 07:14:23 PM PDT 24 Jun 22 07:47:43 PM PDT 24 7494403068 ps
T634 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4086954878 Jun 22 07:10:52 PM PDT 24 Jun 22 07:31:23 PM PDT 24 9301151065 ps
T7 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.608079342 Jun 22 07:34:38 PM PDT 24 Jun 22 07:57:44 PM PDT 24 21110445320 ps
T461 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2631852672 Jun 22 07:48:40 PM PDT 24 Jun 22 07:56:46 PM PDT 24 4915976160 ps
T252 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.144099286 Jun 22 07:11:28 PM PDT 24 Jun 22 10:37:38 PM PDT 24 64544814306 ps
T494 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1428468663 Jun 22 07:47:31 PM PDT 24 Jun 22 07:57:18 PM PDT 24 5275490008 ps
T635 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2083843112 Jun 22 07:26:24 PM PDT 24 Jun 22 07:41:36 PM PDT 24 9173527977 ps
T636 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.283366968 Jun 22 07:14:07 PM PDT 24 Jun 22 07:35:04 PM PDT 24 8297059756 ps
T637 /workspace/coverage/default/2.chip_sw_otbn_randomness.838093803 Jun 22 07:31:11 PM PDT 24 Jun 22 07:45:56 PM PDT 24 5653042672 ps
T339 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2650766612 Jun 22 07:29:55 PM PDT 24 Jun 22 07:34:44 PM PDT 24 3059136284 ps
T638 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1320488970 Jun 22 07:15:23 PM PDT 24 Jun 22 07:20:48 PM PDT 24 2909609186 ps
T464 /workspace/coverage/default/9.chip_sw_all_escalation_resets.3146637981 Jun 22 07:39:49 PM PDT 24 Jun 22 07:51:28 PM PDT 24 4749623768 ps
T639 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.869352020 Jun 22 07:16:36 PM PDT 24 Jun 22 07:38:38 PM PDT 24 7312040486 ps
T187 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3466844074 Jun 22 07:20:01 PM PDT 24 Jun 22 07:44:49 PM PDT 24 6835664244 ps
T640 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1281406969 Jun 22 07:35:39 PM PDT 24 Jun 22 07:42:10 PM PDT 24 2970058900 ps
T641 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3894848491 Jun 22 07:14:11 PM PDT 24 Jun 22 07:20:37 PM PDT 24 3228879289 ps
T642 /workspace/coverage/default/0.chip_sw_example_concurrency.536798635 Jun 22 07:09:42 PM PDT 24 Jun 22 07:14:04 PM PDT 24 3193581384 ps
T13 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2896903398 Jun 22 07:12:59 PM PDT 24 Jun 22 07:35:05 PM PDT 24 20429259004 ps
T643 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4008163177 Jun 22 07:30:04 PM PDT 24 Jun 22 07:49:13 PM PDT 24 6373824878 ps
T644 /workspace/coverage/default/2.chip_tap_straps_testunlock0.3200370105 Jun 22 07:34:14 PM PDT 24 Jun 22 07:37:59 PM PDT 24 2847710126 ps
T645 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1309412041 Jun 22 07:12:51 PM PDT 24 Jun 22 07:22:42 PM PDT 24 4352296650 ps
T266 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3512131072 Jun 22 07:31:49 PM PDT 24 Jun 22 07:40:06 PM PDT 24 5290448166 ps
T646 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.520107948 Jun 22 07:30:36 PM PDT 24 Jun 22 07:32:53 PM PDT 24 2654338877 ps
T647 /workspace/coverage/default/2.chip_tap_straps_prod.3950556903 Jun 22 07:34:25 PM PDT 24 Jun 22 07:37:22 PM PDT 24 2526202054 ps
T513 /workspace/coverage/default/83.chip_sw_all_escalation_resets.615637697 Jun 22 07:48:03 PM PDT 24 Jun 22 07:58:42 PM PDT 24 5789034662 ps
T648 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2131560467 Jun 22 07:13:42 PM PDT 24 Jun 22 07:38:38 PM PDT 24 10266203592 ps
T205 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2378338572 Jun 22 07:15:24 PM PDT 24 Jun 22 07:28:01 PM PDT 24 4486721888 ps
T649 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2569010161 Jun 22 07:14:21 PM PDT 24 Jun 22 07:24:34 PM PDT 24 5854667778 ps
T495 /workspace/coverage/default/66.chip_sw_all_escalation_resets.768689636 Jun 22 07:48:02 PM PDT 24 Jun 22 07:57:38 PM PDT 24 4496743556 ps
T650 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2433374947 Jun 22 07:11:53 PM PDT 24 Jun 22 07:17:24 PM PDT 24 2864608964 ps
T651 /workspace/coverage/default/0.chip_sw_uart_smoketest.1400273256 Jun 22 07:14:37 PM PDT 24 Jun 22 07:19:35 PM PDT 24 2533655056 ps
T652 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2948707166 Jun 22 07:11:05 PM PDT 24 Jun 22 07:33:26 PM PDT 24 7618957408 ps
T490 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4273733908 Jun 22 07:48:04 PM PDT 24 Jun 22 07:53:32 PM PDT 24 4484711540 ps
T653 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2346803140 Jun 22 07:10:09 PM PDT 24 Jun 22 07:19:13 PM PDT 24 5531140104 ps
T654 /workspace/coverage/default/2.chip_tap_straps_dev.3874920471 Jun 22 07:34:04 PM PDT 24 Jun 22 07:46:45 PM PDT 24 8108865090 ps
T655 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3444067288 Jun 22 07:18:32 PM PDT 24 Jun 22 08:23:44 PM PDT 24 15089595920 ps
T656 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2965674311 Jun 22 07:35:58 PM PDT 24 Jun 22 07:59:10 PM PDT 24 4853123160 ps
T657 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.4151204827 Jun 22 07:21:50 PM PDT 24 Jun 22 07:26:08 PM PDT 24 3389591665 ps
T307 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.4157231374 Jun 22 07:32:29 PM PDT 24 Jun 22 07:40:59 PM PDT 24 3812080907 ps
T658 /workspace/coverage/default/2.chip_sw_aes_idle.1208441685 Jun 22 07:31:12 PM PDT 24 Jun 22 07:34:18 PM PDT 24 2946243292 ps
T659 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2430205399 Jun 22 07:38:48 PM PDT 24 Jun 22 07:43:58 PM PDT 24 2792952600 ps
T660 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3898932661 Jun 22 07:21:06 PM PDT 24 Jun 22 07:46:23 PM PDT 24 7252229008 ps
T661 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.2058399235 Jun 22 07:10:00 PM PDT 24 Jun 22 07:14:12 PM PDT 24 2856018438 ps
T399 /workspace/coverage/default/6.chip_sw_all_escalation_resets.2275428145 Jun 22 07:39:48 PM PDT 24 Jun 22 07:50:21 PM PDT 24 5699810136 ps
T406 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2347580529 Jun 22 07:43:51 PM PDT 24 Jun 22 07:54:03 PM PDT 24 6068195255 ps
T342 /workspace/coverage/default/68.chip_sw_all_escalation_resets.3976895938 Jun 22 07:46:30 PM PDT 24 Jun 22 07:55:38 PM PDT 24 5203985436 ps
T249 /workspace/coverage/default/1.chip_jtag_mem_access.3978406 Jun 22 07:17:05 PM PDT 24 Jun 22 07:39:46 PM PDT 24 13199886741 ps
T407 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.661929315 Jun 22 07:47:03 PM PDT 24 Jun 22 07:52:41 PM PDT 24 3627659992 ps
T408 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.777664785 Jun 22 07:46:40 PM PDT 24 Jun 22 07:54:00 PM PDT 24 3917456984 ps
T409 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3417794493 Jun 22 07:33:18 PM PDT 24 Jun 22 07:39:37 PM PDT 24 3484259352 ps
T287 /workspace/coverage/default/1.chip_sw_plic_sw_irq.2680900969 Jun 22 07:22:29 PM PDT 24 Jun 22 07:27:41 PM PDT 24 2879187916 ps
T410 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.856251025 Jun 22 07:29:11 PM PDT 24 Jun 22 08:58:47 PM PDT 24 46711781240 ps
T411 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3145381133 Jun 22 07:47:41 PM PDT 24 Jun 22 07:54:03 PM PDT 24 3594863772 ps
T662 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3939116252 Jun 22 07:35:53 PM PDT 24 Jun 22 08:43:05 PM PDT 24 24829270807 ps
T258 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2454050261 Jun 22 07:33:55 PM PDT 24 Jun 22 07:40:16 PM PDT 24 3654537000 ps
T663 /workspace/coverage/default/2.chip_sw_power_idle_load.2955158627 Jun 22 07:36:21 PM PDT 24 Jun 22 07:46:22 PM PDT 24 4337312170 ps
T664 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2411066062 Jun 22 07:19:57 PM PDT 24 Jun 22 07:43:06 PM PDT 24 6335666884 ps
T523 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1086733206 Jun 22 07:45:22 PM PDT 24 Jun 22 07:50:54 PM PDT 24 2936510874 ps
T267 /workspace/coverage/default/0.chip_sw_flash_init.2136490791 Jun 22 07:09:40 PM PDT 24 Jun 22 07:53:41 PM PDT 24 20225290976 ps
T665 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3304680254 Jun 22 07:39:50 PM PDT 24 Jun 22 08:00:42 PM PDT 24 8415368331 ps
T10 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.4255222089 Jun 22 07:30:43 PM PDT 24 Jun 22 07:34:34 PM PDT 24 3234855360 ps
T432 /workspace/coverage/default/74.chip_sw_all_escalation_resets.874007585 Jun 22 07:48:06 PM PDT 24 Jun 22 07:59:38 PM PDT 24 5595732742 ps
T433 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1810143805 Jun 22 07:34:19 PM PDT 24 Jun 22 07:43:25 PM PDT 24 5365937280 ps
T376 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1381702973 Jun 22 07:12:32 PM PDT 24 Jun 22 07:23:41 PM PDT 24 5498779924 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%