Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3797362	1			T70	141		T71	4142		T72	9653
values[2]	763321	1			T70	10		T71	583		T72	1563
values[3]	106183	1			T71	57		T72	173		T77	14
values[4]	57186	1			T71	70		T72	121		T77	2
values[5]	38716	1			T71	61		T72	84		T356	112
values[6]	28740	1			T71	69		T72	46		T356	110
values[7]	22978	1			T71	84		T72	49		T356	58
values[8]	19375	1			T71	73		T72	42		T356	70
values[9]	17285	1			T71	77		T72	48		T356	84
values[10]	15556	1			T71	71		T72	29		T356	74
values[11]	14573	1			T71	76		T72	22		T356	89
values[12]	13960	1			T71	71		T72	33		T356	89
values[13]	12734	1			T71	57		T72	15		T356	76
values[14]	12209	1			T71	75		T72	17		T356	55
values[15]	12062	1			T71	71		T72	24		T356	42
values[16]	11288	1			T71	69		T72	15		T356	36
values[17]	11325	1			T71	43		T72	22		T356	24
values[18]	10674	1			T71	36		T72	18		T356	32
values[19]	10375	1			T71	67		T72	8		T356	49
values[20]	10157	1			T71	64		T72	7		T356	40
values[21]	9887	1			T71	73		T72	8		T356	43
values[22]	9281	1			T71	84		T72	3		T356	37
values[23]	9036	1			T71	82		T72	2		T356	27
values[24]	8592	1			T71	43		T72	1		T356	31
values[25]	8427	1			T71	41		T72	3		T356	15
values[26]	7653	1			T71	50		T72	1		T356	11
values[27]	7319	1			T71	57		T72	1		T356	8
values[28]	7051	1			T71	42		T72	2		T356	11
values[29]	6542	1			T71	36		T72	1		T356	12
values[30]	6120	1			T71	29		T72	1		T356	18
values[31]	5831	1			T71	28		T72	1		T356	9
values[32]	5543	1			T71	57		T72	4		T356	7
values[33]	5198	1			T71	44		T72	5		T356	15
values[34]	4880	1			T71	14		T72	4		T356	13
values[35]	4508	1			T71	12		T72	2		T356	4
values[36]	4344	1			T71	16		T72	7		T356	4
values[37]	4100	1			T71	15		T72	3		T356	9
values[38]	3822	1			T71	24		T72	7		T356	5
values[39]	3672	1			T71	16		T72	1		T356	6
values[40]	3683	1			T71	28		T72	3		T356	7
values[41]	3470	1			T71	3		T72	2		T356	6
values[42]	3435	1			T71	4		T72	1		T356	5
values[43]	3273	1			T71	8		T72	3		T356	21
values[44]	3266	1			T71	3		T72	4		T356	10
values[45]	3099	1			T71	4		T72	3		T356	3
values[46]	3173	1			T71	1		T72	2		T356	6
values[47]	3022	1			T71	1		T72	2		T356	4
values[48]	3020	1			T71	3		T72	1		T356	4
values[49]	3037	1			T71	3		T72	2		T356	8
values[50]	2912	1			T71	2		T72	8		T356	5
values[51]	2819	1			T71	1		T72	6		T356	4
values[52]	2811	1			T71	4		T72	2		T356	5
values[53]	2704	1			T71	6		T72	1		T356	10
values[54]	2640	1			T71	3		T72	2		T356	8
values[55]	2542	1			T72	2		T356	8		T750	3
values[56]	2506	1			T72	1		T356	9		T750	1
values[57]	2536	1			T72	2		T356	6		T750	3
values[58]	2457	1			T72	6		T356	3		T750	5
values[59]	2496	1			T72	10		T356	2		T750	3
values[60]	2586	1			T72	25		T356	2		T750	1
values[61]	2766	1			T72	20		T356	3		T750	5
values[62]	4109	1			T72	17		T356	8		T750	9
values[63]	11249	1			T72	30		T356	44		T750	39
values[64]	229346	1			T72	29		T356	133		T750	44

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4839596	1			T70	152		T71	5748		T72	12309
values[2]	818640	1			T70	10		T71	1116		T72	1704
values[3]	86144	1			T70	1		T71	30		T72	216
values[4]	14790	1			T71	5		T72	10		T356	5
values[5]	5497	1			T509	1		T484	22		T587	4
values[6]	3418	1			T509	1		T484	13		T587	1
values[7]	2736	1			T509	6		T484	11		T587	1
values[8]	2471	1			T509	2		T484	8		T587	2
values[9]	2221	1			T509	2		T484	7		T587	2
values[10]	1871	1			T509	3		T484	11		T587	3
values[11]	1707	1			T509	1		T484	13		T587	2
values[12]	1592	1			T509	1		T484	8		T587	2
values[13]	1481	1			T509	1		T484	7		T587	2
values[14]	1438	1			T509	3		T484	4		T587	2
values[15]	1393	1			T509	5		T484	3		T587	2
values[16]	1307	1			T509	3		T484	7		T587	3
values[17]	1198	1			T509	2		T484	8		T587	2
values[18]	1148	1			T509	1		T484	21		T587	2
values[19]	1056	1			T509	1		T484	14		T587	2
values[20]	951	1			T509	4		T484	5		T587	2
values[21]	875	1			T509	1		T484	6		T587	2
values[22]	872	1			T509	1		T484	5		T587	2
values[23]	863	1			T509	2		T484	2		T587	2
values[24]	886	1			T509	2		T484	2		T587	2
values[25]	905	1			T509	3		T484	1		T587	2
values[26]	844	1			T509	3		T484	2		T587	2
values[27]	801	1			T509	3		T484	1		T587	2
values[28]	809	1			T509	4		T484	3		T587	2
values[29]	739	1			T509	6		T484	7		T587	2
values[30]	681	1			T509	3		T484	1		T587	2
values[31]	666	1			T509	1		T484	4		T587	2
values[32]	649	1			T509	1		T484	1		T587	2
values[33]	611	1			T509	1		T484	3		T587	2
values[34]	571	1			T509	2		T484	7		T587	2
values[35]	588	1			T509	1		T484	3		T587	2
values[36]	601	1			T509	1		T484	1		T587	2
values[37]	603	1			T509	1		T484	3		T587	2
values[38]	568	1			T509	1		T484	4		T587	2
values[39]	562	1			T509	2		T484	16		T587	2
values[40]	515	1			T509	1		T484	19		T587	2
values[41]	469	1			T509	1		T484	5		T587	2
values[42]	458	1			T509	2		T587	2		T856	1
values[43]	496	1			T509	4		T587	1		T856	1
values[44]	472	1			T509	2		T587	1		T856	1
values[45]	428	1			T509	2		T587	2		T856	1
values[46]	406	1			T509	1		T587	2		T856	1
values[47]	404	1			T509	1		T587	2		T856	1
values[48]	442	1			T509	3		T587	2		T856	1
values[49]	448	1			T509	2		T587	2		T856	1
values[50]	431	1			T509	1		T587	2		T856	1
values[51]	396	1			T509	1		T587	1		T856	1
values[52]	358	1			T509	3		T587	2		T856	1
values[53]	349	1			T509	1		T587	2		T856	1
values[54]	370	1			T509	2		T587	2		T856	1
values[55]	382	1			T509	1		T587	2		T856	1
values[56]	369	1			T509	2		T587	2		T856	1
values[57]	386	1			T509	1		T587	2		T856	1
values[58]	363	1			T509	1		T587	2		T856	1
values[59]	346	1			T509	2		T587	2		T856	1
values[60]	376	1			T509	3		T587	2		T856	1
values[61]	422	1			T509	1		T587	2		T856	1
values[62]	634	1			T509	10		T587	2		T856	1
values[63]	2400	1			T509	24		T587	5		T856	1
values[64]	25927	1			T509	93		T587	88		T856	185

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	568256	1			T70	13		T71	28		T72	1383
values[2]	2676463	1			T70	84		T71	4096		T72	3715
values[3]	1231029	1			T70	14		T71	491		T72	5977
values[4]	154031	1			T70	2		T71	87		T72	507
values[5]	79163	1			T71	73		T72	242		T77	13
values[6]	51053	1			T71	56		T72	164		T77	2
values[7]	36965	1			T71	42		T72	137		T356	75
values[8]	29078	1			T71	85		T72	107		T356	83
values[9]	24581	1			T71	66		T72	73		T356	74
values[10]	22021	1			T71	71		T72	66		T356	44
values[11]	19680	1			T71	78		T72	29		T356	69
values[12]	18143	1			T71	86		T72	26		T356	70
values[13]	16737	1			T71	67		T72	59		T356	76
values[14]	15473	1			T71	46		T72	49		T356	76
values[15]	14793	1			T71	67		T72	25		T356	80
values[16]	13748	1			T71	90		T72	22		T356	64
values[17]	13278	1			T71	61		T72	7		T356	43
values[18]	12944	1			T71	62		T72	5		T356	57
values[19]	12249	1			T71	76		T72	4		T356	34
values[20]	11573	1			T71	70		T72	4		T356	39
values[21]	11242	1			T71	51		T72	6		T356	30
values[22]	10657	1			T71	40		T72	5		T356	28
values[23]	10385	1			T71	43		T72	3		T356	32
values[24]	9946	1			T71	55		T72	5		T356	26
values[25]	9738	1			T71	67		T72	4		T356	15
values[26]	9059	1			T71	62		T72	6		T356	8
values[27]	8699	1			T71	61		T72	1		T356	4
values[28]	8165	1			T71	44		T72	3		T356	5
values[29]	7693	1			T71	35		T72	1		T356	4
values[30]	7295	1			T71	49		T72	1		T356	14
values[31]	6781	1			T71	57		T72	2		T356	28
values[32]	6180	1			T71	56		T72	8		T356	35
values[33]	5556	1			T71	37		T72	5		T356	16
values[34]	5185	1			T71	30		T72	3		T356	10
values[35]	4958	1			T71	19		T72	1		T356	6
values[36]	4649	1			T71	12		T72	1		T356	3
values[37]	4428	1			T71	8		T72	2		T356	5
values[38]	4274	1			T71	11		T72	1		T356	8
values[39]	4070	1			T71	22		T72	3		T356	16
values[40]	3973	1			T71	9		T72	9		T356	7
values[41]	4009	1			T71	7		T72	2		T356	7
values[42]	3892	1			T71	5		T72	11		T356	5
values[43]	3703	1			T71	5		T72	1		T356	3
values[44]	3730	1			T71	2		T72	2		T356	3
values[45]	3565	1			T71	2		T72	7		T356	3
values[46]	3686	1			T71	6		T72	2		T356	5
values[47]	3447	1			T71	2		T72	1		T356	2
values[48]	3415	1			T71	5		T72	3		T356	2
values[49]	3400	1			T71	5		T72	11		T356	9
values[50]	3473	1			T71	2		T72	5		T356	8
values[51]	3333	1			T71	3		T72	1		T356	4
values[52]	3300	1			T71	1		T72	1		T356	3
values[53]	3160	1			T71	3		T72	1		T356	2
values[54]	3149	1			T71	1		T72	2		T356	3
values[55]	2989	1			T72	3		T356	2		T704	5
values[56]	2985	1			T72	6		T356	2		T704	5
values[57]	2933	1			T72	9		T356	4		T704	12
values[58]	2860	1			T72	6		T356	4		T704	1
values[59]	2900	1			T72	5		T356	8		T704	4
values[60]	2870	1			T72	1		T356	6		T704	3
values[61]	2936	1			T72	1		T356	6		T750	1
values[62]	3770	1			T72	1		T356	9		T750	9
values[63]	9698	1			T72	2		T356	55		T750	29
values[64]	218560	1			T72	10		T356	166		T750	25