Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2527124	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32376763

1

T4

28987

T5

14064

T18

4989

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	24069636	1			T4	11930		T5	5987		T18	1908
values[0x0]	9061797	1			T4	17057		T5	8077		T18	3081
values[0x1]	1772454	1			T4	1765		T5	1028		T18	314

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	828303	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34075584

1

T4

30752

T5

15092

T18

5303

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15938085	1			T4	15377		T5	7547		T18	2652
valid_sources[0x01]	15937148	1			T4	15375		T5	7545		T18	2651
valid_sources[0x02]	48056	1			T142	141		T511	24		T143	711
valid_sources[0x03]	48504	1			T193	1		T142	197		T511	35
valid_sources[0x04]	48814	1			T7	6		T142	188		T511	15
valid_sources[0x05]	48330	1			T142	193		T511	12		T143	782
valid_sources[0x06]	47727	1			T193	1		T142	154		T511	18
valid_sources[0x07]	48447	1			T74	7		T193	1		T142	151
valid_sources[0x08]	48908	1			T193	2		T142	150		T511	22
valid_sources[0x09]	47684	1			T7	3		T142	154		T511	20
valid_sources[0x0a]	48188	1			T74	7		T7	2		T142	227
valid_sources[0x0b]	61485	1			T194	39		T142	203		T511	40
valid_sources[0x0c]	48511	1			T75	39		T7	2		T142	138
valid_sources[0x0d]	48227	1			T142	142		T511	13		T143	880
valid_sources[0x0e]	49091	1			T7	2		T193	3		T142	241
valid_sources[0x0f]	48260	1			T142	220		T511	23		T143	706
valid_sources[0x10]	48411	1			T142	195		T511	29		T143	912
valid_sources[0x11]	48458	1			T142	167		T511	35		T143	775
valid_sources[0x12]	47962	1			T7	2		T193	2		T142	174
valid_sources[0x13]	47848	1			T7	1		T193	4		T142	125
valid_sources[0x14]	48558	1			T142	153		T511	23		T143	746
valid_sources[0x15]	48321	1			T142	256		T511	28		T143	945
valid_sources[0x16]	47876	1			T193	1		T142	135		T511	27
valid_sources[0x17]	48208	1			T74	2		T193	1		T142	143
valid_sources[0x18]	48505	1			T7	1		T142	151		T511	31
valid_sources[0x19]	48712	1			T142	210		T511	23		T143	849
valid_sources[0x1a]	48874	1			T142	182		T511	27		T143	805
valid_sources[0x1b]	48921	1			T142	201		T511	30		T143	772
valid_sources[0x1c]	48281	1			T193	2		T142	218		T511	34
valid_sources[0x1d]	48469	1			T142	102		T511	20		T143	846
valid_sources[0x1e]	48599	1			T193	1		T142	247		T511	24
valid_sources[0x1f]	48260	1			T142	133		T511	27		T143	733
valid_sources[0x20]	48971	1			T7	1		T193	2		T142	170

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23071913

1

T4

11930

T5

5987

T18

1908

values[0x0]

all_enables

biggest_size

9023065

1

T4

17057

T5

8077

T18

3081

values[0x1]

all_enables

biggest_size

281785

1

T74

23

T75

18

T76

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3010844	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

476808

1

T70

14

T71

21

T72

1708

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1180322	1			T70	54		T71	147		T72	4106
values[0x0]	1127004	1			T70	47		T71	34		T72	4053
values[0x1]	1180326	1			T70	50		T71	123		T72	4062

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2331826	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1155826

1

T70

40

T71

116

T72

4117

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52928	1			T71	9		T72	91		T77	3
valid_sources[0x01]	54360	1			T71	5		T72	175		T77	11
valid_sources[0x02]	54131	1			T71	3		T72	212		T77	4
valid_sources[0x03]	53447	1			T70	1		T71	4		T72	77
valid_sources[0x04]	54913	1			T70	4		T71	7		T72	155
valid_sources[0x05]	55103	1			T71	2		T72	311		T77	5
valid_sources[0x06]	53949	1			T71	6		T72	180		T77	6
valid_sources[0x07]	54729	1			T71	7		T72	177		T77	6
valid_sources[0x08]	54189	1			T71	9		T72	208		T77	8
valid_sources[0x09]	55776	1			T71	4		T72	182		T77	4
valid_sources[0x0a]	55962	1			T71	7		T72	187		T77	2
valid_sources[0x0b]	53935	1			T71	3		T72	165		T77	1
valid_sources[0x0c]	53857	1			T70	2		T71	3		T72	211
valid_sources[0x0d]	54332	1			T70	2		T71	9		T72	209
valid_sources[0x0e]	54600	1			T71	2		T72	145		T77	5
valid_sources[0x0f]	53368	1			T71	4		T72	116		T77	3
valid_sources[0x10]	55650	1			T70	1		T71	3		T72	219
valid_sources[0x11]	54771	1			T70	6		T71	3		T72	149
valid_sources[0x12]	55060	1			T70	5		T71	1		T72	168
valid_sources[0x13]	53749	1			T70	2		T71	4		T72	151
valid_sources[0x14]	53753	1			T70	4		T71	14		T72	125
valid_sources[0x15]	55512	1			T71	3		T72	180		T77	5
valid_sources[0x16]	54930	1			T70	4		T71	4		T72	111
valid_sources[0x17]	54526	1			T70	1		T71	2		T72	278
valid_sources[0x18]	53623	1			T71	4		T72	151		T77	4
valid_sources[0x19]	54730	1			T70	1		T71	1		T72	198
valid_sources[0x1a]	53929	1			T70	17		T71	5		T72	236
valid_sources[0x1b]	54158	1			T70	1		T71	8		T72	296
valid_sources[0x1c]	55060	1			T71	4		T72	136		T77	5
valid_sources[0x1d]	55435	1			T70	5		T71	2		T72	198
valid_sources[0x1e]	55518	1			T70	8		T71	8		T72	178
valid_sources[0x1f]	55379	1			T71	5		T72	208		T77	4
valid_sources[0x20]	54004	1			T70	3		T71	3		T72	248

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49815

1

T70

2

T71

6

T72

172

values[0x0]

all_enables

biggest_size

377160

1

T70

11

T71

11

T72

1382

values[0x1]

all_enables

biggest_size

49833

1

T70

1

T71

4

T72

154

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3210948	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

524200

1

T70

17

T71

34

T72

1997

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1277346	1			T70	57		T71	173		T72	4759
values[0x0]	1180709	1			T70	46		T71	21		T72	4618
values[0x1]	1277093	1			T70	60		T71	115		T72	4850

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2463878	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1271270

1

T70

48

T71

124

T72

4804

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57522	1			T70	1		T71	6		T72	144
valid_sources[0x01]	58860	1			T70	1		T71	4		T72	151
valid_sources[0x02]	57168	1			T71	6		T72	129		T77	5
valid_sources[0x03]	58486	1			T71	1		T72	177		T77	4
valid_sources[0x04]	57438	1			T71	7		T72	276		T77	7
valid_sources[0x05]	58373	1			T70	3		T71	6		T72	212
valid_sources[0x06]	58974	1			T70	9		T71	4		T72	198
valid_sources[0x07]	57860	1			T70	2		T71	4		T72	231
valid_sources[0x08]	58151	1			T71	5		T72	226		T77	5
valid_sources[0x09]	59248	1			T70	2		T71	6		T72	306
valid_sources[0x0a]	59424	1			T70	6		T71	4		T72	288
valid_sources[0x0b]	57829	1			T71	3		T72	149		T77	3
valid_sources[0x0c]	56746	1			T70	10		T71	1		T72	164
valid_sources[0x0d]	58101	1			T70	1		T71	4		T72	248
valid_sources[0x0e]	58851	1			T70	10		T71	6		T72	178
valid_sources[0x0f]	58107	1			T70	4		T71	7		T72	307
valid_sources[0x10]	58519	1			T70	9		T71	7		T72	344
valid_sources[0x11]	58885	1			T71	6		T72	178		T77	2
valid_sources[0x12]	58141	1			T71	5		T72	230		T77	4
valid_sources[0x13]	58526	1			T70	3		T71	3		T72	212
valid_sources[0x14]	58520	1			T70	3		T71	2		T72	252
valid_sources[0x15]	58574	1			T70	1		T71	6		T72	239
valid_sources[0x16]	57772	1			T70	2		T71	7		T72	360
valid_sources[0x17]	58359	1			T70	5		T71	7		T72	197
valid_sources[0x18]	57764	1			T70	3		T71	5		T72	99
valid_sources[0x19]	58131	1			T71	9		T72	248		T77	3
valid_sources[0x1a]	58028	1			T70	2		T71	5		T72	222
valid_sources[0x1b]	58826	1			T70	8		T71	5		T72	319
valid_sources[0x1c]	57922	1			T71	5		T72	179		T77	3
valid_sources[0x1d]	58790	1			T71	4		T72	290		T77	5
valid_sources[0x1e]	58157	1			T71	5		T72	252		T77	4
valid_sources[0x1f]	59597	1			T70	1		T71	1		T72	187
valid_sources[0x20]	57941	1			T70	1		T71	6		T72	228

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54758

1

T70

2

T71

20

T72

195

values[0x0]

all_enables

biggest_size

415008

1

T70

14

T71

6

T72

1607

values[0x1]

all_enables

biggest_size

54434

1

T70

1

T71

8

T72

195

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3033309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

478400

1

T70

11

T71

32

T72

1687

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1189227	1			T70	37		T71	150		T72	4323
values[0x0]	1134232	1			T70	35		T71	21		T72	4105
values[0x1]	1188250	1			T70	41		T71	151		T72	4312

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2347548	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1164161

1

T70

34

T71

116

T72

4156

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54409	1			T71	3		T72	162		T77	4
valid_sources[0x01]	54940	1			T71	10		T72	220		T77	4
valid_sources[0x02]	54448	1			T70	8		T71	8		T72	186
valid_sources[0x03]	54035	1			T70	23		T71	4		T72	190
valid_sources[0x04]	54788	1			T71	4		T72	218		T77	5
valid_sources[0x05]	54768	1			T71	1		T72	204		T77	7
valid_sources[0x06]	55717	1			T71	2		T72	174		T77	4
valid_sources[0x07]	55298	1			T70	9		T71	6		T72	205
valid_sources[0x08]	54935	1			T71	7		T72	194		T77	3
valid_sources[0x09]	55403	1			T71	5		T72	177		T77	7
valid_sources[0x0a]	55323	1			T71	5		T72	220		T77	2
valid_sources[0x0b]	54018	1			T70	7		T71	3		T72	206
valid_sources[0x0c]	53298	1			T70	3		T71	5		T72	185
valid_sources[0x0d]	54729	1			T70	1		T71	4		T72	168
valid_sources[0x0e]	55018	1			T71	1		T72	178		T77	3
valid_sources[0x0f]	55025	1			T71	5		T72	213		T77	7
valid_sources[0x10]	55366	1			T70	2		T71	11		T72	212
valid_sources[0x11]	55841	1			T71	3		T72	197		T77	2
valid_sources[0x12]	54441	1			T70	7		T71	7		T72	161
valid_sources[0x13]	54585	1			T71	9		T72	225		T77	9
valid_sources[0x14]	54543	1			T70	2		T71	12		T72	171
valid_sources[0x15]	54636	1			T71	6		T72	230		T77	3
valid_sources[0x16]	54656	1			T71	6		T72	202		T77	2
valid_sources[0x17]	55494	1			T71	4		T72	194		T77	6
valid_sources[0x18]	54855	1			T70	2		T71	6		T72	175
valid_sources[0x19]	55590	1			T71	2		T72	188		T77	1
valid_sources[0x1a]	54398	1			T70	10		T71	7		T72	166
valid_sources[0x1b]	55955	1			T70	3		T71	5		T72	219
valid_sources[0x1c]	54857	1			T71	9		T72	199		T356	13
valid_sources[0x1d]	55435	1			T71	3		T72	197		T77	5
valid_sources[0x1e]	54607	1			T71	4		T72	172		T77	2
valid_sources[0x1f]	56502	1			T71	4		T72	214		T77	7
valid_sources[0x20]	53846	1			T71	5		T72	250		T77	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50262

1

T70

1

T71

14

T72

189

values[0x0]

all_enables

biggest_size

378521

1

T70

10

T71

7

T72

1323

values[0x1]

all_enables

biggest_size

49617

1

T71

11

T72

175

T77

10