Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.18 93.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_i2c0 93.10 93.10
tb.dut.top_earlgrey.u_i2c1 93.14 93.14
tb.dut.top_earlgrey.u_i2c2 93.14 93.14



Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.10 93.10


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.10 93.10


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.14 93.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.14 93.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.14 93.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.14 93.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 54 48 88.89
Total Bits 352 328 93.18
Total Bits 0->1 176 164 93.18
Total Bits 1->0 176 164 93.18

Ports 54 48 88.89
Port Bits 352 328 93.18
Port Bits 0->1 176 164 93.18
Port Bits 1->0 176 164 93.18

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T45 Yes T4,T5,T6 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T206,T207,T380 Yes T206,T207,T380 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T206,T207,T380 Yes T206,T207,T380 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_address[6:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T22,*T73,*T63 Yes T22,T73,T63 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_valid Yes Yes T206,T59,T207 Yes T206,T59,T207 INPUT
tl_o.a_ready Yes Yes T206,T59,T207 Yes T206,T59,T207 OUTPUT
tl_o.d_error Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T206,T207,T380 Yes T206,T59,T207 OUTPUT
tl_o.d_data[31:0] Yes Yes T206,T207,T380 Yes T206,T59,T207 OUTPUT
tl_o.d_sink Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T206,*T207,*T380 Yes T206,T207,T380 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T206,T59,T207 Yes T206,T59,T207 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T5,T78,T337 Yes T5,T78,T337 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T205,T79 Yes T78,T205,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T205,T79 Yes T78,T205,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T5,T78,T337 Yes T5,T78,T337 OUTPUT
cio_scl_i Yes Yes T206,T207,T208 Yes T206,T207,T208 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
cio_sda_i Yes Yes T206,T207,T208 Yes T206,T207,T208 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_fmt_threshold_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_rx_threshold_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_acq_threshold_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_rx_overflow_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_controller_halt_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_scl_interference_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_sda_interference_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_stretch_timeout_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_sda_unstable_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_cmd_complete_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_tx_stretch_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_tx_threshold_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_acq_stretch_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_unexp_stop_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_host_timeout_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0
TotalCoveredPercent
Totals 54 48 88.89
Total Bits 348 324 93.10
Total Bits 0->1 174 162 93.10
Total Bits 1->0 174 162 93.10

Ports 54 48 88.89
Port Bits 348 324 93.10
Port Bits 0->1 174 162 93.10
Port Bits 1->0 174 162 93.10

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T45 Yes T4,T5,T6 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T206,T207,T380 Yes T206,T207,T380 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T206,T207,T380 Yes T206,T207,T380 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_address[6:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T22,*T73,*T63 Yes T22,T73,T63 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_valid Yes Yes T206,T59,T207 Yes T206,T59,T207 INPUT
tl_o.a_ready Yes Yes T206,T59,T207 Yes T206,T59,T207 OUTPUT
tl_o.d_error Yes Yes T71,T72,T77 Yes T71,T72,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T206,T207,T380 Yes T206,T59,T207 OUTPUT
tl_o.d_data[31:0] Yes Yes T206,T207,T380 Yes T206,T59,T207 OUTPUT
tl_o.d_sink Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[5:0] Yes Yes *T71,*T72,*T77 Yes T71,T72,T77 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T71,T72,T77 Yes T70,T71,T72 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T206,*T207,*T380 Yes T206,T207,T380 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T206,T59,T207 Yes T206,T59,T207 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T5,T78,T59 Yes T5,T78,T59 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T205,T79 Yes T78,T205,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T205,T79 Yes T78,T205,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T5,T78,T59 Yes T5,T78,T59 OUTPUT
cio_scl_i Yes Yes T206,T207,T208 Yes T206,T207,T208 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
cio_sda_i Yes Yes T206,T207,T208 Yes T206,T207,T208 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_fmt_threshold_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_rx_threshold_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_acq_threshold_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_rx_overflow_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_controller_halt_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_scl_interference_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_sda_interference_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_stretch_timeout_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_sda_unstable_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_cmd_complete_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_tx_stretch_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_tx_threshold_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_acq_stretch_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_unexp_stop_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_host_timeout_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1
TotalCoveredPercent
Totals 54 48 88.89
Total Bits 350 326 93.14
Total Bits 0->1 175 163 93.14
Total Bits 1->0 175 163 93.14

Ports 54 48 88.89
Port Bits 350 326 93.14
Port Bits 0->1 175 163 93.14
Port Bits 1->0 175 163 93.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T45 Yes T4,T5,T6 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T380,T381,T211 Yes T380,T381,T211 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T380,T381,T211 Yes T380,T381,T211 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_address[6:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[18:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T22,*T73,*T63 Yes T22,T73,T63 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_valid Yes Yes T59,T380,T60 Yes T59,T380,T60 INPUT
tl_o.a_ready Yes Yes T59,T380,T60 Yes T59,T380,T60 OUTPUT
tl_o.d_error Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T211,T313,T321 Yes T211,T313,T321 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T380,T381,T211 Yes T59,T380,T60 OUTPUT
tl_o.d_data[31:0] Yes Yes T380,T381,T211 Yes T59,T380,T60 OUTPUT
tl_o.d_sink Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[5:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T380,*T381,*T211 Yes T380,T381,T211 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T59,T380,T60 Yes T59,T380,T60 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T78,T337,T59 Yes T78,T337,T59 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T205,T79 Yes T78,T205,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T205,T79 Yes T78,T205,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T78,T337,T59 Yes T78,T337,T59 OUTPUT
cio_scl_i Yes Yes T211,T321,T382 Yes T211,T321,T382 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T211,T321,T382 Yes T211,T321,T382 OUTPUT
cio_sda_i Yes Yes T211,T321,T382 Yes T211,T321,T382 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T211,T321,T382 Yes T211,T321,T382 OUTPUT
intr_fmt_threshold_o Yes Yes T211,T313,T321 Yes T211,T313,T321 OUTPUT
intr_rx_threshold_o Yes Yes T211,T313,T321 Yes T211,T313,T321 OUTPUT
intr_acq_threshold_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_rx_overflow_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_controller_halt_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_scl_interference_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_sda_interference_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_stretch_timeout_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_sda_unstable_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_cmd_complete_o Yes Yes T211,T313,T321 Yes T211,T313,T321 OUTPUT
intr_tx_stretch_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_tx_threshold_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_acq_stretch_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_unexp_stop_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_host_timeout_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2
TotalCoveredPercent
Totals 54 48 88.89
Total Bits 350 326 93.14
Total Bits 0->1 175 163 93.14
Total Bits 1->0 175 163 93.14

Ports 54 48 88.89
Port Bits 350 326 93.14
Port Bits 0->1 175 163 93.14
Port Bits 1->0 175 163 93.14

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T45 Yes T4,T5,T6 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T380,T381,T313 Yes T380,T381,T313 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T380,T381,T313 Yes T380,T381,T313 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T18 Yes T4,T5,T18 INPUT
tl_i.a_address[6:0] Yes Yes *T70,*T71,*T72 Yes T70,T71,T72 INPUT
tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T18 Yes T4,T5,T18 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T22,*T73,*T63 Yes T22,T73,T63 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T70,T71,T72 Yes T70,T71,T72 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T74,T75,T76 Yes T74,T75,T76 INPUT
tl_i.a_valid Yes Yes T59,T380,T60 Yes T59,T380,T60 INPUT
tl_o.a_ready Yes Yes T59,T380,T60 Yes T59,T380,T60 OUTPUT
tl_o.d_error Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T313,T322,T323 Yes T313,T322,T323 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T380,T381,T313 Yes T59,T380,T60 OUTPUT
tl_o.d_data[31:0] Yes Yes T380,T381,T313 Yes T59,T380,T60 OUTPUT
tl_o.d_sink Yes Yes T71,T72,T77 Yes T70,T71,T72 OUTPUT
tl_o.d_source[5:0] Yes Yes *T71,*T72,*T77 Yes T70,T71,T72 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T70,T71,T72 Yes T71,T72,T77 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T380,*T381,*T313 Yes T380,T381,T313 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T59,T380,T60 Yes T59,T380,T60 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T78,T59,T205 Yes T78,T59,T205 INPUT
alert_rx_i[0].ping_n Yes Yes T78,T205,T79 Yes T78,T205,T79 INPUT
alert_rx_i[0].ping_p Yes Yes T78,T205,T79 Yes T78,T205,T79 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T78,T59,T205 Yes T78,T59,T205 OUTPUT
cio_scl_i Yes Yes T323,T325,T335 Yes T323,T325,T335 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T323,T325,T335 Yes T323,T325,T335 OUTPUT
cio_sda_i Yes Yes T323,T325,T335 Yes T323,T325,T335 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T323,T325,T335 Yes T323,T325,T335 OUTPUT
intr_fmt_threshold_o Yes Yes T313,T322,T323 Yes T313,T322,T323 OUTPUT
intr_rx_threshold_o Yes Yes T313,T322,T323 Yes T313,T322,T323 OUTPUT
intr_acq_threshold_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_rx_overflow_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_controller_halt_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_scl_interference_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_sda_interference_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_stretch_timeout_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_sda_unstable_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_cmd_complete_o Yes Yes T313,T322,T323 Yes T313,T322,T323 OUTPUT
intr_tx_stretch_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_tx_threshold_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_acq_stretch_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_unexp_stop_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT
intr_host_timeout_o Yes Yes T313,T322,T320 Yes T313,T322,T320 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%