Unified Coverage Report :: Module :: spi_host

Module : spi_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.53			95.53

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_host1	96.30			96.30
tb.dut.top_earlgrey.u_spi_host0	96.59			96.59

---

Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30			96.30

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30			96.30

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59			96.59

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59			96.59

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_host

	Total	Covered	Percent
Totals	46	42	91.30
Total Bits	358	342	95.53
Total Bits 0->1	179	171	95.53
Total Bits 1->0	179	171	95.53

Ports	46	42	91.30
Port Bits	358	342	95.53
Port Bits 0->1	179	171	95.53
Port Bits 1->0	179	171	95.53

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T152,*T239,*T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T152,*T239,*T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T27,T28,T189	Yes	T27,T28,T189	INPUT
tl_i.a_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_o.a_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T239,T380	Yes	T152,T239,T59	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T152,*T239,*T380	Yes	T152,T239,T380	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T205	Yes	T78,T59,T205	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T205,T79	Yes	T78,T205,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T205,T79	Yes	T78,T205,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T205	Yes	T78,T59,T205	OUTPUT
cio_sck_o	Yes	Yes	T46,T26,T27	Yes	T46,T26,T27	OUTPUT
cio_sck_en_o	Yes	Yes	T27,T28,T189	Yes	T46,T26,T27	OUTPUT
cio_csb_o	Yes	Yes	T46,T26,T27	Yes	T46,T26,T27	OUTPUT
cio_csb_en_o	Yes	Yes	T27,T28,T189	Yes	T46,T26,T27	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T46,T26,T27	Yes	T46,T26,T27	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T46,*T26,*T27	Yes	T46,T26,T27	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T46,T26,T27	Yes	T46,T26,T27	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T27,*T28,*T189	Yes	T27,T28,T189	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T22,T30,T63	Yes	T22,T23,T30	INPUT
passthrough_i.csb_en	No	No		No		INPUT
passthrough_i.csb	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	INPUT
passthrough_i.sck_en	No	No		No		INPUT
passthrough_i.sck	Yes	Yes	T22,T30,T63	Yes	T22,T30,T63	INPUT
passthrough_i.passthrough_en	Yes	Yes	T27,T28,T189	Yes	T27,T28,T189	INPUT
passthrough_o.s[3:0]	Yes	Yes	T46,T26,T27	Yes	T46,T26,T27	OUTPUT
intr_error_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_spi_event_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1

	Total	Covered	Percent
Totals	38	36	94.74
Total Bits	324	312	96.30
Total Bits 0->1	162	156	96.30
Total Bits 1->0	162	156	96.30

Ports	38	36	94.74
Port Bits	324	312	96.30
Port Bits 0->1	162	156	96.30
Port Bits 1->0	162	156	96.30

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T152,*T239,*T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T152,*T239,*T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_i.a_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_o.a_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T239,T380	Yes	T152,T239,T59	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T152,*T239,*T380	Yes	T152,T239,T380	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T205	Yes	T78,T59,T205	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T205,T79	Yes	T78,T205,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T205,T79	Yes	T78,T205,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T205	Yes	T78,T59,T205	OUTPUT
cio_sck_o	Yes	Yes	T46	Yes	T46	OUTPUT
cio_sck_en_o	Yes	Yes	T142,T143,T144	Yes	T46,T142,T143	OUTPUT
cio_csb_o	Yes	Yes	T46	Yes	T46	OUTPUT
cio_csb_en_o	Yes	Yes	T142,T143,T144	Yes	T46,T142,T143	OUTPUT
cio_sd_o[0]	Yes	Yes	*T46	Yes	T46	OUTPUT
cio_sd_o[3:1]	No	No		No		OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T46	Yes	T46	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T46,T389,T388	Yes	T46,T26,T47	INPUT
passthrough_i.s_en[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.s[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.passthrough_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_o.s[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_error_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_spi_event_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0

	Total	Covered	Percent
Totals	44	42	95.45
Total Bits	352	340	96.59
Total Bits 0->1	176	170	96.59
Total Bits 1->0	176	170	96.59

Ports	44	42	95.45
Port Bits	352	340	96.59
Port Bits 0->1	176	170	96.59
Port Bits 1->0	176	170	96.59

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T152,*T239,*T59	Yes	T152,T239,T59	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T27,T28,T189	Yes	T27,T28,T189	INPUT
tl_i.a_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_o.a_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T239,T380	Yes	T152,T239,T59	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T152,*T239,*T380	Yes	T152,T239,T380	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T205	Yes	T78,T59,T205	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T205,T79	Yes	T78,T205,T79	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T205,T79	Yes	T78,T205,T79	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T205	Yes	T78,T59,T205	OUTPUT
cio_sck_o	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
cio_sck_en_o	Yes	Yes	T27,T28,T189	Yes	T26,T27,T28	OUTPUT
cio_csb_o	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
cio_csb_en_o	Yes	Yes	T27,T28,T189	Yes	T26,T27,T28	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T26,*T27,*T28	Yes	T26,T27,T28	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T27,*T28,*T189	Yes	T27,T28,T189	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T22,T30,T63	Yes	T22,T23,T30	INPUT
passthrough_i.csb_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.csb	Yes	Yes	T22,T23,T30	Yes	T22,T23,T30	INPUT
passthrough_i.sck_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.sck	Yes	Yes	T22,T30,T63	Yes	T22,T30,T63	INPUT
passthrough_i.passthrough_en	Yes	Yes	T27,T28,T189	Yes	T27,T28,T189	INPUT
passthrough_o.s[3:0]	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
intr_error_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
intr_spi_event_o	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT

*Tests covering at least one bit in the range