Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470871947	53171608	0	0
DepthKnown_A	470871947	470768770	0	0
RvalidKnown_A	470871947	470768770	0	0
WreadyKnown_A	470871947	470768770	0	0
gen_passthru_fifo.paramCheckPass	991	991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	53171608	0	0
T4	592568	70280	0	0
T5	239282	31389	0	0
T6	38991	0	0	0
T18	83411	8956	0	0
T19	99076	12943	0	0
T20	171780	25141	0	0
T45	372865	55758	0	0
T58	0	25607	0	0
T62	605119	71815	0	0
T82	276695	36272	0	0
T83	168879	12916	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470871947	40897920	0	0
DepthKnown_A	470871947	470768770	0	0
RvalidKnown_A	470871947	470768770	0	0
WreadyKnown_A	470871947	470768770	0	0
gen_passthru_fifo.paramCheckPass	991	991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	40897920	0	0
T4	592568	52860	0	0
T5	239282	21817	0	0
T6	38991	0	0	0
T18	83411	7026	0	0
T19	99076	9743	0	0
T20	171780	16773	0	0
T45	372865	46826	0	0
T58	0	22934	0	0
T62	605119	54405	0	0
T82	276695	26657	0	0
T83	168879	8688	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470871947	35682734	0	0
DepthKnown_A	470871947	470768770	0	0
RvalidKnown_A	470871947	470768770	0	0
WreadyKnown_A	470871947	470768770	0	0
gen_passthru_fifo.paramCheckPass	991	991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	35682734	0	0
T4	592568	31591	0	0
T5	239282	15475	0	0
T6	38991	0	0	0
T18	83411	5420	0	0
T19	99076	6334	0	0
T20	171780	13198	0	0
T45	372865	42477	0	0
T58	0	5562	0	0
T62	605119	32755	0	0
T82	276695	18990	0	0
T83	168879	6387	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	470871947	31878279	0	0
DepthKnown_A	470871947	470768770	0	0
RvalidKnown_A	470871947	470768770	0	0
WreadyKnown_A	470871947	470768770	0	0
gen_passthru_fifo.paramCheckPass	991	991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	31878279	0	0
T4	592568	30752	0	0
T5	239282	15092	0	0
T6	38991	0	0	0
T18	83411	5303	0	0
T19	99076	6187	0	0
T20	171780	12516	0	0
T45	372865	41822	0	0
T58	0	5358	0	0
T62	605119	31920	0	0
T82	276695	18609	0	0
T83	168879	6142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	470871947	470768770	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	991	991	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	554927355	101327	0	0
DepthKnown_A	554927355	554811664	0	0
RvalidKnown_A	554927355	554811664	0	0
WreadyKnown_A	554927355	554811664	0	0
gen_passthru_fifo.paramCheckPass	2882	2882	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	101327	0	0
T4	592568	112	0	0
T5	239282	151	0	0
T6	38991	0	0	0
T18	83411	13	0	0
T19	99076	16	0	0
T20	171780	34	0	0
T45	372865	42	0	0
T58	0	78	0	0
T62	605119	112	0	0
T82	276695	151	0	0
T83	168879	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2882	2882	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	554927355	103176	0	0
DepthKnown_A	554927355	554811664	0	0
RvalidKnown_A	554927355	554811664	0	0
WreadyKnown_A	554927355	554811664	0	0
gen_passthru_fifo.paramCheckPass	2882	2882	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	103176	0	0
T4	592568	112	0	0
T5	239282	151	0	0
T6	38991	0	0	0
T18	83411	13	0	0
T19	99076	16	0	0
T20	171780	34	0	0
T45	372865	42	0	0
T58	0	78	0	0
T62	605119	112	0	0
T82	276695	151	0	0
T83	168879	30	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2882	2882	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	554927355	52882	0	0
DepthKnown_A	554927355	554811664	0	0
RvalidKnown_A	554927355	554811664	0	0
WreadyKnown_A	554927355	554811664	0	0
gen_passthru_fifo.paramCheckPass	2882	2882	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	52882	0	0
T4	592568	97	0	0
T5	239282	95	0	0
T6	38991	0	0	0
T18	83411	12	0	0
T19	99076	13	0	0
T20	171780	32	0	0
T45	372865	40	0	0
T58	0	77	0	0
T62	605119	97	0	0
T82	276695	95	0	0
T83	168879	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2882	2882	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	554927355	52882	0	0
DepthKnown_A	554927355	554811664	0	0
RvalidKnown_A	554927355	554811664	0	0
WreadyKnown_A	554927355	554811664	0	0
gen_passthru_fifo.paramCheckPass	2882	2882	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	52882	0	0
T4	592568	97	0	0
T5	239282	95	0	0
T6	38991	0	0	0
T18	83411	12	0	0
T19	99076	13	0	0
T20	171780	32	0	0
T45	372865	40	0	0
T58	0	77	0	0
T62	605119	97	0	0
T82	276695	95	0	0
T83	168879	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2882	2882	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	554927355	48445	0	0
DepthKnown_A	554927355	554811664	0	0
RvalidKnown_A	554927355	554811664	0	0
WreadyKnown_A	554927355	554811664	0	0
gen_passthru_fifo.paramCheckPass	2882	2882	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	48445	0	0
T4	592568	15	0	0
T5	239282	56	0	0
T6	38991	0	0	0
T18	83411	1	0	0
T19	99076	3	0	0
T20	171780	2	0	0
T45	372865	2	0	0
T58	0	1	0	0
T62	605119	15	0	0
T82	276695	56	0	0
T83	168879	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2882	2882	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	554927355	50294	0	0
DepthKnown_A	554927355	554811664	0	0
RvalidKnown_A	554927355	554811664	0	0
WreadyKnown_A	554927355	554811664	0	0
gen_passthru_fifo.paramCheckPass	2882	2882	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	50294	0	0
T4	592568	15	0	0
T5	239282	56	0	0
T6	38991	0	0	0
T18	83411	1	0	0
T19	99076	3	0	0
T20	171780	2	0	0
T45	372865	2	0	0
T58	0	1	0	0
T62	605119	15	0	0
T82	276695	56	0	0
T83	168879	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	554927355	554811664	0	0
T4	592568	592284	0	0
T5	239282	239173	0	0
T6	38991	38933	0	0
T18	83411	83356	0	0
T19	99076	99018	0	0
T20	171780	171667	0	0
T45	372865	372755	0	0
T62	605119	604824	0	0
T82	276695	276582	0	0
T83	168879	168759	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2882	2882	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T45	1	1	0	0
T62	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0