Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.94			97.94

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon	99.64			99.64
tb.dut.top_earlgrey.u_sram_ctrl_main	99.65			99.65

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.64			99.64

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.64			99.64

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.65			99.65

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.65			99.65

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	66	60	90.91
Total Bits	1164	1140	97.94
Total Bits 0->1	582	570	97.94
Total Bits 1->0	582	570	97.94

Ports	66	60	90.91
Port Bits	1164	1140	97.94
Port Bits 0->1	582	570	97.94
Port Bits 1->0	582	570	97.94

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[16:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
ram_tl_i.a_address[20:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[27:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
ram_tl_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_address[23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T54,*T112,*T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
regs_tl_i.a_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_o.a_ready	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T112,T170,T113	Yes	T112,T170,T113	OUTPUT
regs_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T73,T247,T70	OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T112,*T170,*T113	Yes	T112,T170,T417	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T155	Yes	T78,T79,T155	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T155	Yes	T78,T79,T155	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	INPUT
sram_otp_key_o.req	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T5,T19,T45	Yes	T5,T19,T45	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T18,T19	Yes	T4,T45,T20	INPUT
sram_otp_key_i.ack	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

	Total	Covered	Percent
Totals	60	58	96.67
Total Bits	1102	1098	99.64
Total Bits 0->1	551	549	99.64
Total Bits 1->0	551	549	99.64

Ports	60	58	96.67
Port Bits	1102	1098	99.64
Port Bits 0->1	551	549	99.64
Port Bits 1->0	551	549	99.64

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[11:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
ram_tl_i.a_address[20:12]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	OUTPUT
ram_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	OUTPUT
ram_tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	OUTPUT
ram_tl_o.d_source[5:0]	Yes	Yes	*T75,*T193,*T194	Yes	T75,T193,T194	OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
regs_tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
regs_tl_i.a_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_o.a_ready	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T112,T170,T113	Yes	T112,T170,T113	OUTPUT
regs_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T112,*T170,*T113	Yes	T112,T170,T417	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T155	Yes	T78,T79,T155	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T155	Yes	T78,T79,T155	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
lc_hw_debug_en_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_sram_ifetch_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
sram_otp_key_o.req	Yes	Yes	T112,T170,T113	Yes	T112,T170,T113	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T5,T19,T45	Yes	T5,T19,T45	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T18,T19	Yes	T4,T45,T20	INPUT
sram_otp_key_i.ack	Yes	Yes	T112,T170,T113	Yes	T112,T170,T113	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

	Total	Covered	Percent
Totals	62	60	96.77
Total Bits	1136	1132	99.65
Total Bits 0->1	568	566	99.65
Total Bits 1->0	568	566	99.65

Ports	62	60	96.77
Port Bits	1136	1132	99.65
Port Bits 0->1	568	566	99.65
Port Bits 1->0	568	566	99.65

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
clk_otp_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_otp_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
ram_tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[16:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
ram_tl_i.a_address[27:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_address[31:29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[2:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
ram_tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
ram_tl_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_user.instr_type[3:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_address[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T54,*T112,*T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T54,*T112,*T170	Yes	T54,T112,T170	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T73,*T247,*T70	Yes	T73,T247,T70	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
regs_tl_i.a_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
regs_tl_o.a_ready	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_user.data_intg[6:0]	Yes	Yes	T298,T299,T300	Yes	T298,T299,T300	OUTPUT
regs_tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	OUTPUT
regs_tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T73,T247,T70	OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T112,*T170,*T113	Yes	T112,T170,T417	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	INPUT
sram_otp_key_o.req	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T5,T19,T45	Yes	T5,T19,T45	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T4,T18,T19	Yes	T4,T45,T20	INPUT
sram_otp_key_i.ack	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range