Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	INPUT
tl_o.a_ready	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T70,*T71	Yes	T76,T70,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T296,*T209,*T145	Yes	T296,T209,T145	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T709,T258	Yes	T78,T709,T258	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T156	Yes	T78,T79,T156	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T156	Yes	T78,T79,T156	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T709,T258	Yes	T78,T709,T258	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
cio_tx_o	Yes	Yes	T209,T145,T54	Yes	T209,T145,T54	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
intr_tx_empty_o	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
intr_rx_watermark_o	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
intr_tx_done_o	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
intr_rx_overflow_o	Yes	Yes	T296,T209,T145	Yes	T296,T209,T145	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T296,T54,T57	Yes	T296,T54,T57	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T296,T54,T57	Yes	T296,T54,T57	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T296,T54,T57	Yes	T296,T54,T57	INPUT
tl_o.a_ready	Yes	Yes	T296,T54,T55	Yes	T296,T54,T55	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T296,T239,T212	Yes	T296,T239,T212	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T296,T54,T55	Yes	T296,T54,T55	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T296,T54,T55	Yes	T296,T54,T55	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T70,*T71	Yes	T76,T70,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T296,*T54,*T55	Yes	T296,T54,T55	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T296,T54,T55	Yes	T296,T54,T55	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T286	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T286	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT
cio_rx_i	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
cio_tx_o	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T296,T239,T212	Yes	T296,T239,T212	OUTPUT
intr_tx_empty_o	Yes	Yes	T296,T212,T213	Yes	T296,T212,T213	OUTPUT
intr_rx_watermark_o	Yes	Yes	T296,T212,T213	Yes	T296,T212,T213	OUTPUT
intr_tx_done_o	Yes	Yes	T296,T212,T213	Yes	T296,T212,T213	OUTPUT
intr_rx_overflow_o	Yes	Yes	T296,T212,T213	Yes	T296,T212,T213	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	INPUT
tl_o.a_ready	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T71,*T72	Yes	T76,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T296,*T209,*T117	Yes	T296,T209,T117	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T156	Yes	T78,T79,T156	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T156	Yes	T78,T79,T156	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T59,T60	Yes	T78,T59,T60	OUTPUT
cio_rx_i	Yes	Yes	T209,T117,T210	Yes	T209,T117,T210	INPUT
cio_tx_o	Yes	Yes	T209,T117,T210	Yes	T209,T117,T210	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
intr_tx_empty_o	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
intr_rx_watermark_o	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
intr_tx_done_o	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
intr_rx_overflow_o	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T296,T145,T59	Yes	T296,T145,T59	INPUT
tl_o.a_ready	Yes	Yes	T296,T145,T59	Yes	T296,T145,T59	OUTPUT
tl_o.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T59	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T59	OUTPUT
tl_o.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T71,*T72	Yes	T76,T71,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T296,*T145,*T146	Yes	T296,T145,T146	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T296,T145,T59	Yes	T296,T145,T59	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T709,T59	Yes	T78,T709,T59	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T316	Yes	T78,T79,T316	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T316	Yes	T78,T79,T316	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T709,T59	Yes	T78,T709,T59	OUTPUT
cio_rx_i	Yes	Yes	T145,T146,T319	Yes	T145,T146,T319	INPUT
cio_tx_o	Yes	Yes	T145,T146,T319	Yes	T145,T146,T319	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	OUTPUT
intr_tx_empty_o	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	OUTPUT
intr_rx_watermark_o	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	OUTPUT
intr_tx_done_o	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	OUTPUT
intr_rx_overflow_o	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	INPUT
tl_o.a_ready	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T76,*T70,*T71	Yes	T76,T70,T71	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T296,*T29,*T30	Yes	T296,T29,T30	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T78,T258,T59	Yes	T78,T258,T59	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T155	Yes	T78,T79,T155	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T155	Yes	T78,T79,T155	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T78,T258,T59	Yes	T78,T258,T59	OUTPUT
cio_rx_i	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cio_tx_o	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
intr_tx_empty_o	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
intr_rx_watermark_o	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
intr_tx_done_o	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
intr_rx_overflow_o	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_break_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_timeout_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T296,T312,T314	Yes	T296,T312,T314	OUTPUT

*Tests covering at least one bit in the range