Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T70,T72,T77	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T217,T73,T218	Yes	T217,T73,T218	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T217,T73,T218	Yes	T217,T73,T218	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T75,T7,T71	Yes	T75,T7,T71	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T75,T7,T70	Yes	T75,T7,T70	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T22,T67,T73	Yes	T22,T67,T73	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T22,T67,T73	Yes	T22,T67,T73	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T22,T67,T73	Yes	T22,T67,T73	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T22,T67,T63	Yes	T22,T67,T63	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T22,T67,T73	Yes	T22,T67,T73	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T67,T68,T64	Yes	T67,T68,T64	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T22,*T67,*T73	Yes	T22,T67,T73	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T22,T67,T73	Yes	T22,T67,T73	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T7,T71,T72	Yes	T7,T71,T72	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T7,T70,T72	Yes	T7,T70,T71	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T7,T71,T72	Yes	T7,T71,T72	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T7,*T71,*T72	Yes	T7,T71,T72	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T7,T71,T72	Yes	T7,T71,T72	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T73,*T246,*T247	Yes	T73,T246,T247	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T18	Yes	T4,T5,T45	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T45	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T73,*T246,*T247	Yes	T73,T246,T247	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T45	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T73,T246,T247	Yes	T73,T246,T247	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T54,T22,T166	Yes	T54,T22,T166	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T54,T166,T55	Yes	T54,T166,T55	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T7	Yes	T59,T60,T7	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T343,T396,T59	Yes	T343,T396,T59	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T343,T396,T59	Yes	T343,T396,T59	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T59,T60,T7	Yes	T59,T60,T7	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T343,T396,T59	Yes	T343,T396,T59	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T7,*T70,*T71	Yes	T7,T70,T71	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T343,T396,T59	Yes	T343,T396,T59	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T343,T396,T59	Yes	T343,T396,T59	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T397,T265,T266	Yes	T397,T265,T266	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T7,T70,T71	Yes	T59,T60,T7	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T397,T265,T266	Yes	T59,T60,T397	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T7,*T70,*T71	Yes	T7,T70,T71	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T343,*T396,*T265	Yes	T343,T396,T397	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T343,T396,T59	Yes	T343,T396,T59	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_peri_i.d_error	Yes	Yes	T5,T217,T688	Yes	T5,T217,T688	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_peri_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T22,*T63,*T357	Yes	T22,T73,T63	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T27,T28,T189	Yes	T27,T28,T189	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T239,T380	Yes	T152,T239,T59	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T152,*T239,*T380	Yes	T152,T239,T380	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T152,T59,T380	Yes	T152,T59,T380	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T239,T380	Yes	T152,T239,T59	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T152,T380,T381	Yes	T152,T380,T381	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T152,*T239,*T380	Yes	T152,T239,T380	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T152,T239,T59	Yes	T152,T239,T59	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T296,T32,T59	Yes	T296,T32,T59	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T76,*T70,*T71	Yes	T76,T70,T71	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	INPUT
tl_usbdev_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T76,*T70,*T71	Yes	T76,T70,T71	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T296,*T32,*T239	Yes	T296,T32,T239	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T296,T32,T239	Yes	T296,T32,T239	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T45	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T70,T72,T77	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T18	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T5,T19	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T19,T54,T284	Yes	T19,T54,T284	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T19,T54,T284	Yes	T19,T54,T284	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T19,T83,T187	Yes	T19,T83,T187	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T19,T54,T284	Yes	T19,T54,T284	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T19,T83,T187	Yes	T19,T83,T187	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T19,T284,T333	Yes	T19,T284,T333	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T19,T83,T187	Yes	T19,T83,T187	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T19,T83,T187	Yes	T19,T83,T187	INPUT
tl_hmac_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T19,T83,T187	Yes	T19,T83,T187	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T83,T187	Yes	T19,T83,T187	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T19,T54,T284	Yes	T19,T54,T284	INPUT
tl_hmac_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T19,*T54,*T284	Yes	T19,T54,T284	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T19,T83,T187	Yes	T19,T83,T187	INPUT
tl_kmac_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T45,T366,T421	Yes	T45,T366,T421	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T20,T83	Yes	T45,T20,T83	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T45,T20,T83	Yes	T45,T20,T83	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T45,T366,T421	Yes	T45,T366,T421	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T45,T20,T83	Yes	T45,T20,T83	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T45,T366,T421	Yes	T45,T366,T421	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T45,T20,T83	Yes	T45,T20,T83	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T45,T20,T83	Yes	T45,T20,T83	INPUT
tl_kmac_i.d_error	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T45,T20,T187	Yes	T45,T20,T187	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T20,T187	Yes	T45,T20,T187	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T45,T20,T366	Yes	T45,T20,T366	INPUT
tl_kmac_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T45,*T20,*T366	Yes	T45,T20,T366	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T45,T20,T187	Yes	T45,T20,T187	INPUT
tl_aes_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T726,T687,T259	Yes	T726,T687,T259	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T726,T687,T259	Yes	T726,T687,T259	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T83,T187,T248	Yes	T83,T187,T248	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T726,T687,T259	Yes	T726,T687,T259	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T83,T187,T248	Yes	T83,T187,T248	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T74,*T71,*T72	Yes	T74,T71,T72	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T83,T187,T248	Yes	T83,T187,T248	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T83,T248,T249	Yes	T83,T248,T249	INPUT
tl_aes_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T83,T248,T249	Yes	T83,T248,T249	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T248,T249,T250	Yes	T248,T249,T250	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T83,T248,T249	Yes	T83,T248,T249	INPUT
tl_aes_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T74,*T71,*T72	Yes	T74,T71,T72	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T83,*T248,*T249	Yes	T83,T248,T249	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T83,T248,T249	Yes	T83,T248,T249	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T45,*T122,*T108	Yes	T45,T54,T122	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T45,T122,T691	Yes	T45,T122,T691	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T74,*T70,*T71	Yes	T74,T70,T71	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_csrng_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T45,T122,T691	Yes	T45,T122,T691	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_csrng_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T74,*T71,*T72	Yes	T74,T70,T71	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T45,*T122,*T691	Yes	T45,T122,T691	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_edn0_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_edn0_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T45,*T122,*T108	Yes	T45,T122,T108	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_edn1_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	INPUT
tl_edn1_i.d_error	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	INPUT
tl_edn1_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T71,T72,T77	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T45,*T122,*T108	Yes	T45,T122,T108	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T45,T122,T108	Yes	T45,T122,T108	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T19	Yes	T4,T5,T19	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T174,T54,T122	Yes	T174,T54,T122	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T83,T187,T174	Yes	T83,T187,T174	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T83,T187,T174	Yes	T83,T187,T174	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T174,T54,T122	Yes	T174,T54,T122	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T83,T187,T174	Yes	T83,T187,T174	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T75,*T193,*T194	Yes	T75,T193,T194	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T83,T187,T174	Yes	T83,T187,T174	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T83,T187,T174	Yes	T83,T187,T174	INPUT
tl_otbn_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T174,T54,T122	Yes	T174,T54,T122	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T83,T187,T174	Yes	T83,T187,T174	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T83,T187,T174	Yes	T83,T187,T174	INPUT
tl_otbn_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T75,*T193,*T194	Yes	T75,T193,T194	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T174,*T54,*T122	Yes	T174,T54,T122	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T83,T187,T174	Yes	T83,T187,T174	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T45,T20,T57	Yes	T45,T20,T57	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	INPUT
tl_keymgr_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T45,*T20,*T54	Yes	T45,T20,T54	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T45,T20,T54	Yes	T45,T20,T54	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T7,*T71,*T72	Yes	T7,T71,T72	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T7,T70,T71	Yes	T7,T71,T72	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T5,T19	Yes	T4,T5,T19	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T7,*T70,*T71	Yes	T7,T70,T71	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T73,*T247,*T70	Yes	T73,T247,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T298,T299,T300	Yes	T298,T299,T300	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T73,T247,T70	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T112,*T170,*T113	Yes	T112,T170,T417	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range