Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_main_o.d_error	Yes	Yes	T5,T217,T688	Yes	T5,T217,T688	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_main_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T22,*T63,*T357	Yes	T22,T73,T63	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T296,T54,T57	Yes	T296,T54,T57	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T296,T54,T57	Yes	T296,T54,T57	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T296,T54,T57	Yes	T296,T54,T57	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T296,T54,T55	Yes	T296,T54,T55	INPUT
tl_uart0_i.d_error	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T296,T239,T212	Yes	T296,T239,T212	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T296,T54,T55	Yes	T296,T54,T55	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T296,T54,T55	Yes	T296,T54,T55	INPUT
tl_uart0_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T76,*T70,*T71	Yes	T76,T70,T71	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T296,*T54,*T55	Yes	T296,T54,T55	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T296,T54,T55	Yes	T296,T54,T55	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	INPUT
tl_uart1_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	INPUT
tl_uart1_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T76,*T71,*T72	Yes	T76,T71,T72	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T296,*T209,*T117	Yes	T296,T209,T117	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T296,T209,T117	Yes	T296,T209,T117	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T296,T145,T59	Yes	T296,T145,T59	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T296,T145,T59	Yes	T296,T145,T59	INPUT
tl_uart2_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T146	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T59	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T296,T145,T146	Yes	T296,T145,T59	INPUT
tl_uart2_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T76,*T71,*T72	Yes	T76,T71,T72	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T296,*T145,*T146	Yes	T296,T145,T146	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T296,T145,T59	Yes	T296,T145,T59	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	INPUT
tl_uart3_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	INPUT
tl_uart3_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T76,*T70,*T71	Yes	T76,T70,T71	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T296,*T29,*T30	Yes	T296,T29,T30	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T296,T29,T30	Yes	T296,T29,T30	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T206,T207,T380	Yes	T206,T207,T380	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T206,T207,T380	Yes	T206,T207,T380	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T206,T59,T207	Yes	T206,T59,T207	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T206,T59,T207	Yes	T206,T59,T207	INPUT
tl_i2c0_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T206,T207,T208	Yes	T206,T207,T208	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T206,T207,T380	Yes	T206,T59,T207	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T206,T207,T380	Yes	T206,T59,T207	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T206,*T207,*T380	Yes	T206,T207,T380	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T206,T59,T207	Yes	T206,T59,T207	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T380,T381,T211	Yes	T380,T381,T211	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T380,T381,T211	Yes	T380,T381,T211	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T59,T380,T60	Yes	T59,T380,T60	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T59,T380,T60	Yes	T59,T380,T60	INPUT
tl_i2c1_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T211,T313,T321	Yes	T211,T313,T321	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T380,T381,T211	Yes	T59,T380,T60	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T380,T381,T211	Yes	T59,T380,T60	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T380,*T381,*T211	Yes	T380,T381,T211	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T59,T380,T60	Yes	T59,T380,T60	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T380,T381,T313	Yes	T380,T381,T313	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T380,T381,T313	Yes	T380,T381,T313	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T59,T380,T60	Yes	T59,T380,T60	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T59,T380,T60	Yes	T59,T380,T60	INPUT
tl_i2c2_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T313,T322,T323	Yes	T313,T322,T323	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T380,T381,T313	Yes	T59,T380,T60	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T380,T381,T313	Yes	T59,T380,T60	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T70,T71,T72	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T380,*T381,*T313	Yes	T380,T381,T313	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T59,T380,T60	Yes	T59,T380,T60	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	INPUT
tl_pattgen_i.d_error	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T152,T153,T154	Yes	T152,T153,T154	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T153,T154	Yes	T152,T59,T60	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T152,T153,T154	Yes	T152,T59,T60	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T152,*T153,*T154	Yes	T152,T153,T154	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T147,T148,T727	Yes	T147,T148,T727	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T147,T148,T727	Yes	T147,T148,T727	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T59,T60,T147	Yes	T59,T60,T147	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T59,T60,T147	Yes	T59,T60,T147	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T147,T148,T727	Yes	T147,T148,T727	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T147,T148,T727	Yes	T59,T60,T147	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T147,T148,T727	Yes	T59,T60,T147	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T7,*T70,*T71	Yes	T7,T70,T71	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T147,*T148,*T727	Yes	T147,T148,T727	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T59,T60,T147	Yes	T59,T60,T147	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_gpio_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T39,T40,T313	Yes	T39,T40,T313	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T147,T39,T40	Yes	T59,T60,T147	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T147,T39,T40	Yes	T59,T60,T147	INPUT
tl_gpio_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T71,*T72,*T77	Yes	T71,T72,T77	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T45	Yes	T4,T5,T18	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T22,T152,T30	Yes	T22,T152,T30	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T22,T152,T30	Yes	T22,T152,T30	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T22,T152,T30	Yes	T22,T152,T30	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T22,T152,T30	Yes	T22,T152,T30	INPUT
tl_spi_device_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T22,T152,T30	Yes	T22,T152,T30	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T22,T152,T30	Yes	T22,T152,T30	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T22,T152,T30	Yes	T22,T152,T30	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T22,*T152,*T30	Yes	T22,T152,T30	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T22,T152,T30	Yes	T22,T152,T30	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T152,T147,T153	Yes	T152,T147,T153	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T152,T147,T153	Yes	T152,T147,T153	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T152,T153,T733	Yes	T152,T153,T733	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T152,T147,T153	Yes	T152,T59,T60	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T147,T148,T733	Yes	T152,T59,T60	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T71,T72,T77	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T152,*T147,*T153	Yes	T152,T147,T153	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T62,T82	Yes	T4,T62,T82	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T62,T82	Yes	T4,T62,T82	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T4,T62,T82	Yes	T4,T62,T82	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T4,T62,T82	Yes	T4,T62,T82	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T62,T82	Yes	T4,T62,T82	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T62,T83	Yes	T4,T62,T83	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T62,T82	Yes	T4,T62,T82	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T7,*T71,*T72	Yes	T7,T70,T71	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T62,*T83	Yes	T4,T62,T82	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T4,T62,T82	Yes	T4,T62,T82	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T7,*T71,*T72	Yes	T7,T71,T72	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T18,T83,T58	Yes	T18,T83,T58	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T18,T19,T83	Yes	T18,T19,T83	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T18,T58,T29	Yes	T18,T58,T29	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T74,*T71,*T72	Yes	T74,T71,T72	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T18,*T83,*T58	Yes	T18,T83,T58	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T7,*T71,*T72	Yes	T7,T71,T72	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T22,*T63,*T151	Yes	T22,T63,T151	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T45,*T20,*T22	Yes	T45,T20,T22	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T18	Yes	T4,T5,T45	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T45	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T45	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T20,T164,T54	Yes	T20,T164,T54	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T20,T164,T54	Yes	T20,T164,T54	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T20,T164,T54	Yes	T20,T164,T54	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T20,T164,T54	Yes	T20,T164,T54	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T72,T77,T356	Yes	T70,T72,T77	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T20,T54,T22	Yes	T20,T164,T54	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T98,T102,T163	Yes	T59,T98,T102	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T20,T54,T22	Yes	T20,T164,T54	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T357,*T358,*T359	Yes	T357,T358,T359	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T20,*T22,*T30	Yes	T20,T164,T54	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T20,T164,T54	Yes	T20,T164,T54	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T121,T152,T1	Yes	T121,T152,T1	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T121,T152,T1	Yes	T121,T152,T59	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T71,T72,T77	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T45	Yes	T4,T5,T18	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T74,*T70,*T71	Yes	T74,T70,T71	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T62	Yes	T4,T5,T62	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T112,T170,T113	Yes	T112,T170,T113	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T112,T170,T113	Yes	T54,T112,T170	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T112,*T170,*T113	Yes	T112,T170,T417	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T54,T112,T170	Yes	T54,T112,T170	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T4,T5,T45	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T45	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T75,*T193,*T194	Yes	T75,T193,T194	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T74,*T71,*T72	Yes	T73,T246,T74	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T62	Yes	T4,T5,T62	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T4,T5,T62	Yes	T4,T5,T62	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T62,T296	Yes	T4,T62,T296	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T62,T296	Yes	T4,T62,T296	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T4,T62,T296	Yes	T4,T62,T296	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T4,T62,T296	Yes	T4,T62,T296	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T62,T296	Yes	T4,T62,T296	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T62,T296	Yes	T4,T62,T296	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T4,T62,T431	Yes	T4,T62,T296	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T76,*T70,*T71	Yes	T76,T71,T72	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T4,*T62,*T296	Yes	T4,T62,T296	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T4,T62,T296	Yes	T4,T62,T296	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T59,T1,T2	Yes	T59,T1,T2	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T59,T1,T2	Yes	T59,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T59,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T59,T1,T2	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T74,*T70,*T71	Yes	T74,T70,T71	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T59,T1,T2	Yes	T59,T1,T2	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_ast_i.d_error	Yes	Yes	T71,T72,T77	Yes	T70,T71,T72	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T4,T5,T45	Yes	T4,T5,T18	INPUT
tl_ast_i.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T71,T72,T77	Yes	T71,T72,T77	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T71,T72,T77	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T70,*T71,*T72	Yes	T71,T72,T77	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range