Unified Coverage Report :: Module :: rv_timer

Module : rv_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_timer	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rv_timer

	Total	Covered	Percent
Totals	30	30	100.00
Total Bits	292	292	100.00
Total Bits 0->1	146	146	100.00
Total Bits 1->0	146	146	100.00

Ports	30	30	100.00
Port Bits	292	292	100.00
Port Bits 0->1	146	146	100.00
Port Bits 1->0	146	146	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T5,T45	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T152,T147,T153	Yes	T152,T147,T153	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T152,T147,T153	Yes	T152,T147,T153	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[8:0]	Yes	Yes	*T70,*T71,*T72	Yes	T70,T71,T72	INPUT
tl_i.a_address[19:9]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[29:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T18	Yes	T4,T5,T18	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T22,*T73,*T63	Yes	T22,T73,T63	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_i.a_valid	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	INPUT
tl_o.a_ready	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	OUTPUT
tl_o.d_error	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T152,T153,T733	Yes	T152,T153,T733	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T147,T153	Yes	T152,T59,T60	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T147,T148,T733	Yes	T152,T59,T60	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T70,*T71,*T72	Yes	T71,T72,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T71,T72	Yes	T70,T71,T72	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T152,*T147,*T153	Yes	T152,T147,T153	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T152,T59,T60	Yes	T152,T59,T60	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T124,T78,T367	Yes	T124,T78,T367	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T124,T78,T367	Yes	T124,T78,T367	OUTPUT
intr_timer_expired_hart0_timer0_o	Yes	Yes	T152,T153,T244	Yes	T152,T153,T244	OUTPUT

*Tests covering at least one bit in the range