25e609d6bb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 6.477m | 2.882ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.653m | 2.507ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.560m | 2.847ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.966m | 3.188ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 7.277m | 6.384ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 11.523m | 6.208ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 21.680m | 11.720ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.791h | 54.488ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 2.107m | 2.386ms | 0 | 20 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.791h | 54.488ms | 5 | 5 | 100.00 |
| chip_csr_rw | 11.523m | 6.208ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 10.630s | 255.108us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 9.785m | 4.581ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 9.785m | 4.581ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 9.785m | 4.581ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 11.539m | 4.425ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 11.539m | 4.425ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 14.179m | 4.816ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 13.846m | 4.557ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 13.388m | 4.603ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 45.922m | 13.457ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 12.707m | 3.850ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 33.517m | 12.910ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 200 | 220 | 90.91 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 7.418m | 5.014ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 7.418m | 5.014ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 6.384m | 3.822ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.430m | 6.518ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.604m | 3.557ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 13.113m | 7.042ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 10.984m | 7.709ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 17.038m | 9.010ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.317m | 10.024ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.753m | 3.279ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 29.977m | 9.817ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 17.680m | 6.132ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 17.680m | 6.132ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 16.755m | 7.234ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 46.410m | 18.777ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.365m | 4.619ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 20.012m | 6.254ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.226h | 18.729ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.178m | 2.788ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.235m | 6.583ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.734m | 3.174ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.393m | 12.682ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.166m | 2.661ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.102m | 4.632ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.125m | 2.676ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.948m | 3.739ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 15.946m | 7.314ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.295m | 5.401ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.780m | 3.327ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.295m | 5.401ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 5.489m | 3.304ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.095m | 3.735ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.107m | 3.151ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.675m | 3.088ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.710m | 2.804ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.262m | 3.681ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.408m | 2.687ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.332m | 2.809ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 5.243m | 2.462ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 23.188m | 6.349ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.591m | 5.043ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 8.842m | 6.193ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 4.665m | 2.365ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 5.389m | 2.780ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.276m | 2.576ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.257m | 3.225ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.784m | 3.129ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.374m | 3.112ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 11.044m | 5.759ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.751h | 78.886ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.384h | 15.119ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 3.401h | 200.068ms | 0 | 3 | 0.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 13.218m | 4.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 9.142m | 9.513ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.964h | 58.428ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.048h | 64.592ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.053m | 5.540ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.053m | 5.540ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.791h | 54.488ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.373h | 29.870ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.277m | 6.384ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.523m | 6.208ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.791h | 54.488ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.373h | 29.870ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 7.277m | 6.384ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.523m | 6.208ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.616m | 2.558ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.510s | 57.773us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.058m | 10.481ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 1.937m | 6.856ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 54.500s | 580.561us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 21.187m | 117.152ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 20.486m | 70.560ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.128m | 1.493ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 58.150s | 1.387ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.768m | 2.693ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 58.150s | 1.387ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.658m | 3.909ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 49.683m | 151.687ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.367m | 2.867ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 11.190m | 17.562ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 17.008m | 22.398ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 16.468m | 18.472ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 17.657m | 24.168ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.384h | 15.119ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 14.781m | 6.224ms | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 12.223m | 4.500ms | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 1.026h | 12.247ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.316h | 15.027ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.196h | 15.829ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.137h | 16.171ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.159h | 15.130ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 47.274m | 12.297ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 59.354m | 15.429ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 58.298m | 15.524ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.201h | 16.024ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.169h | 15.226ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.450h | 18.563ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.592h | 24.719ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.552h | 24.749ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.717h | 25.024ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.432h | 23.648ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 5.890m | 3.948ms | 0 | 1 | 0.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 13.789m | 5.637ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 14.269m | 5.116ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 12.790m | 5.230ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 11.425m | 5.387ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 6.170m | 3.612ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 10.806m | 5.104ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 13.278m | 5.546ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 14.835m | 5.647ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 11.552m | 4.791ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 6.767m | 3.416ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 16.209m | 4.591ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 15.838m | 5.077ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 14.658m | 5.591ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 11.692m | 4.785ms | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 1.003h | 11.990ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.006h | 15.844ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.179h | 16.312ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.275h | 15.865ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.043h | 15.730ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.001h | 15.322ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.201h | 15.547ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.072h | 15.391ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.390h | 16.997ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.851m | 3.301ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.178m | 2.788ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.250m | 2.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.002m | 2.391ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 36.393m | 12.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.470m | 18.174ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.470m | 18.174ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.104m | 3.777ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 7.591m | 5.043ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.104m | 3.777ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 12.656m | 7.792ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 12.656m | 7.792ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 9.750m | 6.457ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 11.321m | 5.699ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 17.182m | 5.597ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.002m | 2.391ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.699m | 3.606ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.513m | 2.661ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 9.211m | 5.269ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 9.187m | 4.039ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 11.684m | 3.841ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.687m | 5.858ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 31.235m | 11.486ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.727m | 4.067ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.421m | 4.826ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 13.803m | 4.797ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.335m | 4.752ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.626m | 4.566ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.345m | 4.957ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 16.755m | 7.234ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 14.232m | 12.148ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 13.803m | 4.797ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.335m | 4.752ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.365m | 4.619ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 20.012m | 6.254ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.226h | 18.729ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.178m | 2.788ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 20.235m | 6.583ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.734m | 3.174ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.393m | 12.682ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.166m | 2.661ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.102m | 4.632ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.125m | 2.676ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 5.334m | 3.558ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 12.531m | 4.791ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 21.359m | 7.218ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.115h | 24.853ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.636m | 2.841ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.242m | 2.790ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 33.086m | 11.069ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.688m | 2.741ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 10.203m | 4.943ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 33.510m | 17.732ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 1.436h | 26.153ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 16.755m | 7.234ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 11.207m | 4.560ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.567m | 3.572ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 15.049m | 5.886ms | 100 | 100 | 100.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 26.460m | 7.885ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 27.423m | 7.848ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 10.244m | 5.496ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 13.630m | 6.221ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.400m | 2.229ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 23.994m | 9.753ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 33.014m | 24.868ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.249m | 3.279ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.595m | 3.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.306m | 4.796ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 33.014m | 24.868ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 33.014m | 24.868ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 56.962m | 20.416ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 56.962m | 20.416ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.168m | 6.045ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.470m | 18.174ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.598h | 23.582ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 5.115m | 2.952ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 23.164m | 6.786ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.115m | 2.952ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 27.423m | 7.848ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 5.560m | 2.375ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 35.509m | 22.127ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 20.038m | 6.037ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 20.012m | 6.254ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 11.850m | 3.961ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 12.365m | 4.619ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.474h | 43.591ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 35.509m | 22.127ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.689m | 3.195ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 41.854m | 10.934ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.589m | 5.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.474h | 43.591ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.589m | 5.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.589m | 5.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.589m | 5.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.589m | 5.395ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 15.049m | 5.886ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 9.029m | 14.080ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 20.420m | 5.652ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 12.817m | 4.996ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 12.817m | 4.996ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.356m | 3.189ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.734m | 3.174ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.699m | 3.606ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.605m | 2.694ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 29.046m | 6.997ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 15.431m | 5.214ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 17.539m | 5.747ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 16.299m | 5.614ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 13.058m | 4.153ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 41.854m | 10.934ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 41.393m | 12.682ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 31.153m | 8.938ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 36.393m | 12.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.334h | 16.458ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.812m | 3.292ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 4.490m | 2.756ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.166m | 2.661ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 41.854m | 10.934ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.021m | 13.068ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.847m | 2.937ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 5.293m | 2.624ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.513m | 2.661ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.588m | 4.575ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 13.113m | 7.042ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 17.038m | 9.010ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.317m | 10.024ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 6.478m | 2.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.021m | 13.068ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.021m | 13.068ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.021m | 13.068ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 36.211m | 9.763ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.589m | 5.395ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.474h | 43.591ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.166m | 4.522ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 24.138m | 8.552ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 26.372m | 9.205ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 27.473m | 6.962ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.021m | 13.068ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 41.854m | 10.934ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 9.957m | 8.389ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 14.281m | 7.632ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 9.029m | 14.080ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 14.232m | 12.148ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.727m | 4.067ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 12.421m | 4.826ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 13.803m | 4.797ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 13.335m | 4.752ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.626m | 4.566ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.345m | 4.957ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 13.113m | 7.042ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 17.038m | 9.010ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 19.317m | 10.024ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 14.258m | 14.464ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.144m | 2.321ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.240m | 2.807ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.577m | 2.691ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.225m | 3.822ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 44.249m | 34.093ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 14.258m | 14.464ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.738h | 48.788ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.576h | 50.165ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 15.907m | 9.504ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.634h | 47.353ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 44.249m | 34.093ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 1.798m | 2.976ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.014m | 2.753ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 1.958m | 2.551ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.021m | 13.068ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 35.509m | 22.127ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.697m | 3.623ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 41.854m | 10.934ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.389m | 4.491ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.268m | 2.895ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 35.509m | 22.127ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.697m | 3.623ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 41.854m | 10.934ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.389m | 4.491ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.268m | 2.895ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.021m | 13.068ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 15.879m | 15.443ms | 0 | 3 | 0.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 6.478m | 2.703ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.166m | 4.522ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 24.138m | 8.552ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 26.372m | 9.205ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 27.473m | 6.962ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.021m | 13.068ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 9.029m | 14.080ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 9.029m | 14.080ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.663h | 26.846ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.170m | 7.904ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 33.708m | 22.917ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 8.833m | 7.930ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 17.363m | 8.034ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 13.238m | 7.605ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 30.560m | 22.434ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 22.963m | 12.118ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 12.656m | 7.792ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 29.697m | 13.571ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 12.357m | 5.900ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.170m | 7.904ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 7.885m | 4.358ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 59.703m | 36.065ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 11.216m | 6.729ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.168m | 6.489ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 50.672m | 29.076ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 23.994m | 9.753ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 31.080m | 9.932ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 40.022m | 32.814ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.472m | 2.617ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 15.049m | 5.886ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 9.957m | 8.389ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 9.957m | 8.389ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 31.080m | 9.932ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 50.672m | 29.076ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 12.357m | 5.900ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.591m | 5.043ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 9.587m | 5.001ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 15.502m | 7.477ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.791m | 3.905ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 29.053m | 10.516ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.649m | 3.187ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 15.049m | 5.886ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 30.938m | 8.158ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 21.967m | 5.704ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 9.700m | 4.439ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 16.234m | 5.119ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.894m | 3.254ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.337m | 2.724ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.384h | 15.119ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 16.986m | 7.768ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 11.304m | 4.605ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 8.411m | 3.423ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.969m | 2.922ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 11.389m | 4.491ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 10.102m | 4.632ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 16.025m | 8.095ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 13.531m | 7.536ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 14.281m | 7.632ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 15.049m | 5.886ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 17.680m | 6.132ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 4.716m | 3.655ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.227m | 2.510ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 8.787m | 4.019ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.701m | 3.685ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 32.186m | 7.865ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 1.940h | 31.454ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 52.888m | 12.558ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.268m | 2.922ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.588m | 4.575ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 15.049m | 5.886ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.256m | 3.117ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 29.053m | 10.516ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 9.445m | 4.973ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 8.865m | 3.860ms | 87 | 90 | 96.67 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 23.008m | 11.365ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 26.460m | 7.885ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 30.938m | 8.158ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 23.589m | 7.706ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.238h | 254.836ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 46.297m | 22.418ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 25.154m | 13.736ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 9.587m | 5.001ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.520m | 5.645ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 8.629m | 3.893ms | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 17.038m | 9.010ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 14.258m | 14.464ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2611 | 2644 | 98.75 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.928m | 2.644ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 1 | 0.00 | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 3 | 0.00 | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 23.098m | 7.934ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 22.758m | 7.660ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 28.894m | 8.534ms | 0 | 1 | 0.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 56.799m | 44.995ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 44.862m | 32.384ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 57.161m | 30.689ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | ||
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 9.409m | 3.175ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 11.887m | 3.271ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 30.817m | 7.754ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 40.641m | 10.116ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.559m | 3.670ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 19.891m | 5.568ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | //sw/device/tests:i2c_host_override_test | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.216m | 3.100ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 10.846m | 5.874ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 8.362m | 6.226ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 9.726m | 5.344ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 31.080m | 9.932ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 15.049m | 5.886ms | 100 | 100 | 100.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | chip_sw_spi_host_configuration | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 11.539m | 4.425ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.260h | 18.756ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 23.098m | 7.934ms | 0 | 1 | 0.00 |
| rom_e2e_jtag_debug_dev | 22.758m | 7.660ms | 0 | 1 | 0.00 | ||
| rom_e2e_jtag_debug_rma | 28.894m | 8.534ms | 0 | 1 | 0.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 11.186m | 4.481ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 35 | 45 | 77.78 | |||
| Unmapped tests | chip_sival_flash_info_access | 6.145m | 3.091ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 14.399m | 5.744ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 5.214m | 3.473ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.030h | 17.353ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 21.686m | 5.470ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 15.964m | 4.749ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 7.429m | 3.778ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 9.111m | 6.911ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 6.193m | 3.100ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.894m | 2.681ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 6.435m | 3.604ms | 3 | 3 | 100.00 | ||
| TOTAL | 2882 | 2945 | 97.86 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 11 | 100.00 |
| V1 | 18 | 18 | 17 | 94.44 |
| V2 | 285 | 270 | 249 | 87.37 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 21 | 15 | 16.67 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.23 | 95.53 | 94.17 | 95.47 | -- | 95.13 | 97.53 | 99.57 |
UVM_ERROR @ * us: (cip_base_vseq.sv:828) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
0.chip_csr_mem_rw_with_rand_reset.100959469624529811789261378446528590366059193015221545916232783420241279820385
Line 361, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2647.310628 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2647.310628 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_csr_mem_rw_with_rand_reset.103088533912814728840540040083006915805654675647894428735573995091418224540799
Line 372, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2968.246885 us: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2968.246885 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:*-*-* has 15 failures:
Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.88982160617709759643723222428401200405613288494190995063783238843429920409629
Line 1012, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
UVM_ERROR @ 3947.578149 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:07535603
LCV:02108421
"
UVM_INFO @ 3947.578149 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_dev.28782781554251187797184154033359043402668541467899643634683977283135379729721
Line 997, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
UVM_ERROR @ 5637.244031 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:07535603
LCV:21084210
"
UVM_INFO @ 5637.244031 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Test rom_e2e_sigverify_always_a_bad_b_bad_prod has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_prod.14964238832222744973367587557891496950198754495702630977001448489420093492685
Line 1016, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest/run.log
UVM_ERROR @ 5115.922761 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:07535603
LCV:2318c631
"
UVM_INFO @ 5115.922761 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Test rom_e2e_sigverify_always_a_bad_b_bad_prod_end has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.56260471725502958937443215107206127683579623003940107457998378457238590179251
Line 1036, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest/run.log
UVM_ERROR @ 5230.229373 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:07535603
LCV:25294a52
"
UVM_INFO @ 5230.229373 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
Test rom_e2e_sigverify_always_a_bad_b_bad_rma has 1 failures.
0.rom_e2e_sigverify_always_a_bad_b_bad_rma.41242946412877248903688501490011095483483651892373019054585585966545369318436
Line 1024, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest/run.log
UVM_ERROR @ 5387.137305 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:07535603
LCV:2739ce73
"
UVM_INFO @ 5387.137305 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 10 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.72013133299698387535345228810238509991084074737296242094544886870440945458141
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:b52e9a81-e6f4-4967-8172-bb2d729ee60a
1.chip_sw_rv_timer_systick_test.64009586390077207859631666998024404068717999009999626936057891407478496220262
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:1c4fe962-cb1f-4132-b8d5-4ee48f01225b
... and 1 more failures.
Test chip_sw_coremark has 1 failures.
0.chip_sw_coremark.22023440617892367873840736801205293217780184582396101583137941713267092672279
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
Job ID: smart:bd934ac1-fc02-4522-a71b-1d17a1ae1f46
Test chip_sw_power_virus has 3 failures.
0.chip_sw_power_virus.15594183858096984545911607240018379892490118681488563040471938405168566551759
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
Job ID: smart:f1de2a1e-044b-4b69-8bb1-dcc98c72c1f6
1.chip_sw_power_virus.76025882446493602399986854564925134856325897212303198460529367343540782139293
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
Job ID: smart:00f01d02-4864-4fb2-a451-f5373d7e923a
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
0.chip_sw_lc_ctrl_program_error.41506381486400146604946784122515087819303009198694682350818208741472774568386
Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14807.720504 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14807.720504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_lc_ctrl_program_error.85198320874763669885090106236733543390783713371491431564996264282826771082455
Line 782, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
UVM_ERROR @ 14443.258924 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
UVM_INFO @ 14443.258924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep. has 3 failures:
0.chip_sw_rv_dm_access_after_wakeup.67781235065307591479744252261155656721929133682151085997287371074018317432400
Line 837, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 4144.376529 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 4144.376529 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_dm_access_after_wakeup.16811026925333035155867793509062932336440480188569816714125936112250328105032
Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_dm_access_after_wakeup/latest/run.log
UVM_FATAL @ 3142.791879 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to enter normal sleep.
UVM_INFO @ 3142.791879 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
0.rom_e2e_shutdown_exception_c.4856575540452234824468349434423869507143812533404884101371460401565033496844
Line 1088, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
UVM_ERROR @ 4500.100539 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:01495202
LCV:2739ce73
"
UVM_INFO @ 4500.100539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
1.rom_e2e_shutdown_exception_c.68918056348467999946059431263518863777914861010646939390035986379244272932665
Line 983, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
UVM_ERROR @ 4823.686125 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:01495202
LCV:2739ce73
"
UVM_INFO @ 4823.686125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:35) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* has 3 failures:
0.rom_e2e_shutdown_output.45265158786893626682468485440391741371184054194980259946706240763825223208431
Line 960, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
UVM_ERROR @ 7163.878423 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:0142500d
LCV:02108421
"
UVM_INFO @ 7163.878423 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
1.rom_e2e_shutdown_output.85447593254749513084748256398492260002073654149929182774948910401626875008010
Line 947, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
UVM_ERROR @ 6223.594980 us: (chip_sw_rom_e2e_base_vseq.sv:35) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:4001-0002-01
GIT:" == "BFV:0142500d
LCV:02108421
"
UVM_INFO @ 6223.594980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat" has 3 failures:
Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
0.rom_e2e_jtag_debug_test_unlocked0.48907795129653588819774888938247241981915943058431150183734597570738365668410
Line 806, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
UVM_FATAL @ 7934.464918 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
UVM_INFO @ 7934.464918 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_dev has 1 failures.
0.rom_e2e_jtag_debug_dev.59013729461178243438731301064091149519724836189251305854508384389610900676154
Line 845, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
UVM_FATAL @ 7660.218680 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
UVM_INFO @ 7660.218680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_jtag_debug_rma has 1 failures.
0.rom_e2e_jtag_debug_rma.63470765693371079787662282539191517687301937456684884377466067629090688185536
Line 831, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
UVM_FATAL @ 8533.552702 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "uart_putchar.dat"
UVM_INFO @ 8533.552702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
18.chip_sw_alert_handler_lpg_sleep_mode_alerts.115622107709336606185655951374045560446648568653664276145682389639148734694795
Line 848, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3356.857950 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 3356.857950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.chip_sw_alert_handler_lpg_sleep_mode_alerts.89066187863079295233988186026038103644717890877603947863642606265759082513413
Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4018.329896 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 4018.329896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:306) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 2 failures:
0.rom_raw_unlock.28750916846554070416318691478055327537307597064421091950718967138530888436474
Line 798, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
UVM_ERROR @ 206034.114280 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
UVM_INFO @ 206034.114280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rom_raw_unlock.20566455509451227522091809378413085846394156332511523066972074025984313642784
Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log
UVM_ERROR @ 206533.003262 us: (chip_sw_base_vseq.sv:306) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 200000000 ns
UVM_INFO @ 206533.003262 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
1.rom_raw_unlock.55231774109717250188595058289474997034190680518766025001396564952362108299595
Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log
UVM_ERROR @ 200068.081694 us: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
UVM_INFO @ 200068.081694 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---