Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2140553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32063967

1

T4

5673

T5

39

T6

8591

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23212894	1			T4	2346		T6	4182		T18	8681
values[0x0]	9243770	1			T4	3327		T5	18		T6	4409
values[0x1]	1747856	1			T4	350		T5	21		T6	523

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	532659	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33671861

1

T4

6023

T5

39

T6

9114

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16060510	1			T4	3012		T6	4557		T18	11476
valid_sources[0x01]	16059920	1			T4	3011		T6	4557		T18	11472
valid_sources[0x02]	33433	1			T72	3		T189	2		T190	1
valid_sources[0x03]	33603	1			T147	31		T823	9		T510	28
valid_sources[0x04]	33473	1			T147	39		T823	14		T510	26
valid_sources[0x05]	33335	1			T72	2		T189	1		T147	28
valid_sources[0x06]	35537	1			T147	31		T823	9		T510	29
valid_sources[0x07]	33776	1			T147	49		T823	11		T510	24
valid_sources[0x08]	32633	1			T72	2		T147	34		T823	19
valid_sources[0x09]	32629	1			T147	39		T823	11		T510	30
valid_sources[0x0a]	33022	1			T1	1		T72	1		T189	1
valid_sources[0x0b]	33441	1			T147	42		T823	6		T510	22
valid_sources[0x0c]	33554	1			T72	2		T147	40		T823	12
valid_sources[0x0d]	33955	1			T1	3		T189	1		T147	34
valid_sources[0x0e]	33865	1			T147	29		T823	13		T510	25
valid_sources[0x0f]	33863	1			T188	4		T147	36		T823	12
valid_sources[0x10]	33283	1			T189	1		T147	38		T823	14
valid_sources[0x11]	33134	1			T147	40		T823	7		T510	24
valid_sources[0x12]	33363	1			T189	1		T147	39		T823	8
valid_sources[0x13]	37898	1			T72	3		T188	8		T147	29
valid_sources[0x14]	33009	1			T189	3		T147	40		T823	13
valid_sources[0x15]	33501	1			T188	9		T147	38		T823	12
valid_sources[0x16]	33146	1			T189	3		T147	32		T823	19
valid_sources[0x17]	33694	1			T1	3		T190	2		T147	44
valid_sources[0x18]	32920	1			T72	1		T188	3		T189	1
valid_sources[0x19]	33400	1			T147	36		T823	7		T510	29
valid_sources[0x1a]	33065	1			T189	1		T147	26		T823	10
valid_sources[0x1b]	33316	1			T147	47		T823	6		T510	20
valid_sources[0x1c]	32905	1			T147	31		T823	11		T510	25
valid_sources[0x1d]	33767	1			T147	24		T823	7		T510	23
valid_sources[0x1e]	33176	1			T189	2		T147	28		T823	13
valid_sources[0x1f]	33166	1			T5	39		T147	39		T823	19
valid_sources[0x20]	33219	1			T189	1		T147	44		T823	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22616969

1

T4

2346

T6

4182

T18

8681

values[0x0]

all_enables

biggest_size

9208768

1

T4

3327

T5

18

T6

4409

values[0x1]

all_enables

biggest_size

238230

1

T5

21

T1

23

T72

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3000359	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

474013

1

T68

20

T69

434

T70

13

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1176214	1			T68	41		T69	1065		T70	26
values[0x0]	1122176	1			T68	43		T69	1106		T70	30
values[0x1]	1175982	1			T68	37		T69	1122		T70	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2323553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1150819

1

T68

39

T69

1074

T70

29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55822	1			T69	29		T70	2		T73	11
valid_sources[0x01]	54610	1			T68	2		T69	45		T70	1
valid_sources[0x02]	54310	1			T68	1		T69	54		T70	1
valid_sources[0x03]	54257	1			T68	2		T69	48		T70	3
valid_sources[0x04]	54405	1			T68	2		T69	63		T73	12
valid_sources[0x05]	53640	1			T69	66		T70	2		T73	2
valid_sources[0x06]	54375	1			T69	38		T73	12		T122	3
valid_sources[0x07]	53816	1			T69	40		T70	2		T73	2
valid_sources[0x08]	53961	1			T68	2		T69	33		T70	1
valid_sources[0x09]	52977	1			T68	4		T69	59		T73	9
valid_sources[0x0a]	54406	1			T69	53		T70	2		T73	10
valid_sources[0x0b]	54588	1			T68	3		T69	58		T70	3
valid_sources[0x0c]	54600	1			T68	4		T69	68		T70	2
valid_sources[0x0d]	54000	1			T68	2		T69	50		T70	1
valid_sources[0x0e]	55267	1			T68	2		T69	30		T70	2
valid_sources[0x0f]	54354	1			T68	2		T69	75		T70	1
valid_sources[0x10]	54739	1			T68	3		T69	42		T70	1
valid_sources[0x11]	55293	1			T68	5		T69	49		T73	3
valid_sources[0x12]	54527	1			T68	4		T69	52		T70	1
valid_sources[0x13]	53908	1			T69	63		T73	23		T122	3
valid_sources[0x14]	53937	1			T68	1		T69	45		T70	1
valid_sources[0x15]	53667	1			T69	55		T70	1		T73	2
valid_sources[0x16]	55724	1			T68	3		T69	55		T122	4
valid_sources[0x17]	53615	1			T68	2		T69	61		T70	1
valid_sources[0x18]	54507	1			T69	48		T70	1		T73	3
valid_sources[0x19]	54523	1			T68	2		T69	41		T70	1
valid_sources[0x1a]	54467	1			T68	5		T69	57		T70	1
valid_sources[0x1b]	54572	1			T68	6		T69	53		T73	5
valid_sources[0x1c]	54133	1			T68	3		T69	39		T70	2
valid_sources[0x1d]	54171	1			T68	2		T69	59		T73	6
valid_sources[0x1e]	53524	1			T68	3		T69	48		T70	2
valid_sources[0x1f]	53963	1			T68	2		T69	48		T70	2
valid_sources[0x20]	54573	1			T68	1		T69	44		T73	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49559

1

T68

1

T69

25

T73

7

values[0x0]

all_enables

biggest_size

374516

1

T68

16

T69

368

T70

12

values[0x1]

all_enables

biggest_size

49938

1

T68

3

T69

41

T70

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3189518	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

517984

1

T68

20

T69

424

T70

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1270173	1			T68	57		T69	1125		T70	48
values[0x0]	1167576	1			T68	54		T69	978		T70	36
values[0x1]	1269753	1			T68	49		T69	1003		T70	41

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2448570	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1258932

1

T68

48

T69

1036

T70

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57779	1			T68	1		T69	45		T70	3
valid_sources[0x01]	57167	1			T68	2		T69	58		T73	12
valid_sources[0x02]	57459	1			T68	2		T69	66		T70	4
valid_sources[0x03]	58339	1			T68	1		T69	60		T70	1
valid_sources[0x04]	58031	1			T68	1		T69	48		T70	3
valid_sources[0x05]	56602	1			T68	2		T69	40		T70	5
valid_sources[0x06]	56755	1			T68	2		T69	37		T73	8
valid_sources[0x07]	58485	1			T68	3		T69	52		T73	8
valid_sources[0x08]	57620	1			T68	2		T69	47		T70	3
valid_sources[0x09]	56947	1			T68	2		T69	26		T73	9
valid_sources[0x0a]	58028	1			T68	2		T69	43		T70	1
valid_sources[0x0b]	57761	1			T68	4		T69	49		T73	7
valid_sources[0x0c]	58376	1			T68	1		T69	62		T70	6
valid_sources[0x0d]	56707	1			T68	2		T69	44		T70	9
valid_sources[0x0e]	58218	1			T68	5		T69	50		T73	6
valid_sources[0x0f]	58561	1			T68	6		T69	42		T73	8
valid_sources[0x10]	57720	1			T68	6		T69	55		T70	6
valid_sources[0x11]	58426	1			T68	2		T69	49		T73	10
valid_sources[0x12]	57369	1			T68	2		T69	41		T70	4
valid_sources[0x13]	57926	1			T68	3		T69	44		T73	8
valid_sources[0x14]	57519	1			T68	5		T69	53		T70	2
valid_sources[0x15]	58035	1			T68	3		T69	45		T70	2
valid_sources[0x16]	58111	1			T68	3		T69	64		T70	3
valid_sources[0x17]	58176	1			T68	6		T69	53		T73	15
valid_sources[0x18]	59060	1			T68	1		T69	43		T70	1
valid_sources[0x19]	58593	1			T68	2		T69	61		T70	1
valid_sources[0x1a]	58336	1			T68	2		T69	51		T73	12
valid_sources[0x1b]	58469	1			T68	6		T69	54		T73	8
valid_sources[0x1c]	58407	1			T69	50		T70	1		T73	4
valid_sources[0x1d]	58115	1			T69	48		T73	5		T74	109
valid_sources[0x1e]	57979	1			T68	3		T69	49		T70	3
valid_sources[0x1f]	58156	1			T68	2		T69	38		T70	4
valid_sources[0x20]	57599	1			T68	3		T69	49		T73	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54144

1

T68

3

T69

52

T70

3

values[0x0]

all_enables

biggest_size

409429

1

T68

16

T69

328

T70

16

values[0x1]

all_enables

biggest_size

54411

1

T68

1

T69

44

T70

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3031609	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

479980

1

T68

23

T69

440

T70

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1189406	1			T68	41		T69	1127		T70	29
values[0x0]	1134104	1			T68	66		T69	1048		T70	25
values[0x1]	1188079	1			T68	54		T69	1115		T70	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2348071	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1163518

1

T68

51

T69

1068

T70

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55362	1			T68	4		T69	55		T70	6
valid_sources[0x01]	54225	1			T68	3		T69	49		T70	1
valid_sources[0x02]	53529	1			T68	16		T69	46		T73	6
valid_sources[0x03]	54621	1			T68	8		T69	57		T70	4
valid_sources[0x04]	54897	1			T69	61		T70	3		T73	11
valid_sources[0x05]	53921	1			T69	43		T70	2		T73	8
valid_sources[0x06]	55773	1			T68	2		T69	51		T73	10
valid_sources[0x07]	55169	1			T69	49		T70	9		T73	5
valid_sources[0x08]	54969	1			T69	60		T70	2		T73	12
valid_sources[0x09]	53992	1			T69	63		T73	8		T122	1
valid_sources[0x0a]	55312	1			T69	49		T70	2		T73	15
valid_sources[0x0b]	54881	1			T68	10		T69	57		T70	1
valid_sources[0x0c]	55321	1			T68	11		T69	51		T70	1
valid_sources[0x0d]	54404	1			T69	56		T73	7		T122	4
valid_sources[0x0e]	55898	1			T69	61		T73	6		T122	1
valid_sources[0x0f]	55379	1			T69	53		T73	11		T122	5
valid_sources[0x10]	54951	1			T68	8		T69	47		T73	13
valid_sources[0x11]	54974	1			T68	4		T69	48		T70	2
valid_sources[0x12]	54504	1			T69	58		T70	1		T73	4
valid_sources[0x13]	55264	1			T68	6		T69	50		T73	9
valid_sources[0x14]	53990	1			T69	56		T73	10		T122	1
valid_sources[0x15]	55250	1			T69	62		T70	2		T73	4
valid_sources[0x16]	55260	1			T69	51		T70	1		T73	14
valid_sources[0x17]	54503	1			T68	2		T69	42		T73	10
valid_sources[0x18]	55472	1			T68	8		T69	34		T73	12
valid_sources[0x19]	54626	1			T69	48		T70	1		T73	7
valid_sources[0x1a]	54038	1			T69	46		T73	2		T122	2
valid_sources[0x1b]	55245	1			T69	44		T70	1		T73	7
valid_sources[0x1c]	55892	1			T68	7		T69	60		T73	8
valid_sources[0x1d]	53876	1			T69	58		T70	1		T73	6
valid_sources[0x1e]	55343	1			T68	4		T69	55		T73	10
valid_sources[0x1f]	55246	1			T69	47		T70	2		T73	7
valid_sources[0x20]	54474	1			T69	44		T70	1		T73	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50621

1

T68

3

T69

47

T70

2

values[0x0]

all_enables

biggest_size

379109

1

T68

17

T69

349

T70

11

values[0x1]

all_enables

biggest_size

50250

1

T68

3

T69

44

T70

2