Module Definition
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Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.41 99.34 100.00 98.31 100.00 u_pinmux_strap_sampling


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_lc_sync_a 100.00 100.00 100.00
u_prim_lc_sync_b 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_lc_or_hardened
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN6011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' or '../src/lowrisc_prim_lc_or_hardened_0.1/rtl/prim_lc_or_hardened.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
56 4 4
60 1 1


Cond Coverage for Module : prim_lc_or_hardened
TotalCoveredPercent
Conditions2828100.00
Logical2828100.00
Non-Logical00
Event00

 LINE       56
 EXPRESSION ((lc_en_a_copies[0] == ActVal) || (lc_en_b_copies[0] == ActVal))
             --------------1--------------    --------------2--------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[0] == ActVal)
                --------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[0] == ActVal)
                --------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       56
 EXPRESSION ((lc_en_a_copies[1] == ActVal) || (lc_en_b_copies[1] == ActVal))
             --------------1--------------    --------------2--------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[1] == ActVal)
                --------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[1] == ActVal)
                --------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       56
 EXPRESSION ((lc_en_a_copies[2] == ActVal) || (lc_en_b_copies[2] == ActVal))
             --------------1--------------    --------------2--------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[2] == ActVal)
                --------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[2] == ActVal)
                --------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       56
 EXPRESSION ((lc_en_a_copies[3] == ActVal) || (lc_en_b_copies[3] == ActVal))
             --------------1--------------    --------------2--------------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T6

 LINE       56
 SUB-EXPRESSION (lc_en_a_copies[3] == ActVal)
                --------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       56
 SUB-EXPRESSION (lc_en_b_copies[3] == ActVal)
                --------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

Assert Coverage for Module : prim_lc_or_hardened
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FunctionCheck_A 114949128 114296374 0 0
OutputsKnown_A 114949128 114296374 0 0


FunctionCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114949128 114296374 0 0
T4 26476 25967 0 0
T5 51191 50288 0 0
T6 41858 41325 0 0
T18 112345 109307 0 0
T19 60426 59981 0 0
T20 957760 956028 0 0
T80 45908 45159 0 0
T81 18562 17961 0 0
T82 183473 183020 0 0
T83 64420 63952 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 114949128 114296374 0 0
T4 26476 25967 0 0
T5 51191 50288 0 0
T6 41858 41325 0 0
T18 112345 109307 0 0
T19 60426 59981 0 0
T20 957760 956028 0 0
T80 45908 45159 0 0
T81 18562 17961 0 0
T82 183473 183020 0 0
T83 64420 63952 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%