Unified Coverage Report :: Module :: pwm

Module : pwm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwm_0.1/rtl/pwm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pwm_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_pwm_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : pwm

	Total	Covered	Percent
Totals	32	32	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	32	32	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
clk_core_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_core_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	INPUT
tl_i.a_valid	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	INPUT
tl_o.a_ready	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
tl_o.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T1,*T73,*T146	Yes	T1,T68,T70	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T144,*T1,*T205	Yes	T144,T1,T205	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T351,T76,T56	Yes	T351,T76,T56	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T351,T76,T78	Yes	T76,T78,T200	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T76,T78,T200	Yes	T351,T76,T78	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T351,T76,T56	Yes	T351,T76,T56	OUTPUT
cio_pwm_o[5:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
cio_pwm_en_o[5:0]	Unreachable	Unreachable		Unreachable		OUTPUT

*Tests covering at least one bit in the range