Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460254785	51631584	0	0
DepthKnown_A	460254785	460151859	0	0
RvalidKnown_A	460254785	460151859	0	0
WreadyKnown_A	460254785	460151859	0	0
gen_passthru_fifo.paramCheckPass	977	977	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	51631584	0	0
T4	106658	11532	0	0
T5	208140	0	0	0
T6	154966	20935	0	0
T18	438609	38127	0	0
T19	246835	32191	0	0
T20	397861	72241	0	0
T75	0	21095	0	0
T80	181788	20391	0	0
T81	73297	8952	0	0
T82	759423	107198	0	0
T83	261768	27451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	977	977	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460254785	39802791	0	0
DepthKnown_A	460254785	460151859	0	0
RvalidKnown_A	460254785	460151859	0	0
WreadyKnown_A	460254785	460151859	0	0
gen_passthru_fifo.paramCheckPass	977	977	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	39802791	0	0
T4	106658	9514	0	0
T5	208140	0	0	0
T6	154966	15807	0	0
T18	438609	30616	0	0
T19	246835	22685	0	0
T20	397861	36778	0	0
T75	0	16019	0	0
T80	181788	16337	0	0
T81	73297	6101	0	0
T82	759423	100298	0	0
T83	261768	21116	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	977	977	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460254785	35893512	0	0
DepthKnown_A	460254785	460151859	0	0
RvalidKnown_A	460254785	460151859	0	0
WreadyKnown_A	460254785	460151859	0	0
gen_passthru_fifo.paramCheckPass	977	977	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	35893512	0	0
T4	106658	6165	0	0
T5	208140	39	0	0
T6	154966	9392	0	0
T18	438609	23456	0	0
T19	246835	16148	0	0
T20	397861	9138	0	0
T80	181788	16572	0	0
T81	73297	6069	0	0
T82	759423	95407	0	0
T83	261768	15770	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	977	977	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	460254785	32155608	0	0
DepthKnown_A	460254785	460151859	0	0
RvalidKnown_A	460254785	460151859	0	0
WreadyKnown_A	460254785	460151859	0	0
gen_passthru_fifo.paramCheckPass	977	977	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	32155608	0	0
T4	106658	6023	0	0
T5	208140	39	0	0
T6	154966	9114	0	0
T18	438609	22948	0	0
T19	246835	15771	0	0
T20	397861	7488	0	0
T80	181788	16356	0	0
T81	73297	5481	0	0
T82	759423	94993	0	0
T83	261768	15383	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	460151859	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	977	977	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534443494	79760	0	0
DepthKnown_A	534443494	534328315	0	0
RvalidKnown_A	534443494	534328315	0	0
WreadyKnown_A	534443494	534328315	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	79760	0	0
T4	106658	13	0	0
T5	208140	0	0	0
T6	154966	26	0	0
T18	438609	68	0	0
T19	246835	151	0	0
T20	397861	35	0	0
T75	0	26	0	0
T80	181788	56	0	0
T81	73297	34	0	0
T82	759423	39	0	0
T83	261768	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534443494	80267	0	0
DepthKnown_A	534443494	534328315	0	0
RvalidKnown_A	534443494	534328315	0	0
WreadyKnown_A	534443494	534328315	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	80267	0	0
T4	106658	13	0	0
T5	208140	0	0	0
T6	154966	26	0	0
T18	438609	68	0	0
T19	246835	151	0	0
T20	397861	35	0	0
T75	0	26	0	0
T80	181788	56	0	0
T81	73297	34	0	0
T82	759423	39	0	0
T83	261768	75	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534443494	51149	0	0
DepthKnown_A	534443494	534328315	0	0
RvalidKnown_A	534443494	534328315	0	0
WreadyKnown_A	534443494	534328315	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	51149	0	0
T4	106658	12	0	0
T5	208140	0	0	0
T6	154966	23	0	0
T18	438609	64	0	0
T19	246835	95	0	0
T20	397861	35	0	0
T75	0	23	0	0
T80	181788	55	0	0
T81	73297	33	0	0
T82	759423	37	0	0
T83	261768	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534443494	51149	0	0
DepthKnown_A	534443494	534328315	0	0
RvalidKnown_A	534443494	534328315	0	0
WreadyKnown_A	534443494	534328315	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	51149	0	0
T4	106658	12	0	0
T5	208140	0	0	0
T6	154966	23	0	0
T18	438609	64	0	0
T19	246835	95	0	0
T20	397861	35	0	0
T75	0	23	0	0
T80	181788	55	0	0
T81	73297	33	0	0
T82	759423	37	0	0
T83	261768	72	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534443494	28611	0	0
DepthKnown_A	534443494	534328315	0	0
RvalidKnown_A	534443494	534328315	0	0
WreadyKnown_A	534443494	534328315	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	28611	0	0
T4	106658	1	0	0
T5	208140	0	0	0
T6	154966	3	0	0
T18	438609	4	0	0
T19	246835	56	0	0
T20	397861	0	0	0
T53	0	29	0	0
T75	0	3	0	0
T80	181788	1	0	0
T81	73297	1	0	0
T82	759423	2	0	0
T83	261768	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	534443494	29118	0	0
DepthKnown_A	534443494	534328315	0	0
RvalidKnown_A	534443494	534328315	0	0
WreadyKnown_A	534443494	534328315	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	29118	0	0
T4	106658	1	0	0
T5	208140	0	0	0
T6	154966	3	0	0
T18	438609	4	0	0
T19	246835	56	0	0
T20	397861	0	0	0
T53	0	29	0	0
T75	0	3	0	0
T80	181788	1	0	0
T81	73297	1	0	0
T82	759423	2	0	0
T83	261768	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534443494	534328315	0	0
T4	106658	106600	0	0
T5	208140	208027	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0