Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T80,T53	Yes	T5,T80,T53	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T80,T53	Yes	T5,T80,T53	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	INPUT
tl_i.a_valid	Yes	Yes	T5,T80,T53	Yes	T5,T80,T53	INPUT
tl_o.a_ready	Yes	Yes	T5,T80,T53	Yes	T5,T80,T53	OUTPUT
tl_o.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T80,T87	Yes	T5,T80,T87	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T80,T53	Yes	T5,T80,T53	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T80,T53	Yes	T5,T80,T53	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T5,*T189,*T68	Yes	T5,T189,T68	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T80,*T53	Yes	T5,T80,T53	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T80,T53	Yes	T5,T80,T53	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T76,T78,T361	Yes	T76,T78,T153	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T76,T78,T153	Yes	T76,T78,T361	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
cio_rx_i	Yes	Yes	T18,T19,T80	Yes	T4,T6,T18	INPUT
cio_tx_o	Yes	Yes	T5,T80,T53	Yes	T5,T80,T53	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T80,T87	Yes	T5,T80,T87	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T80,T87	Yes	T5,T80,T87	OUTPUT
intr_rx_watermark_o	Yes	Yes	T80,T87,T293	Yes	T80,T87,T293	OUTPUT
intr_tx_done_o	Yes	Yes	T80,T87,T325	Yes	T80,T87,T325	OUTPUT
intr_rx_overflow_o	Yes	Yes	T80,T87,T325	Yes	T80,T87,T325	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	INPUT
tl_i.a_valid	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	INPUT
tl_o.a_ready	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	OUTPUT
tl_o.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T87,T293	Yes	T5,T87,T293	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T5,*T189,*T68	Yes	T5,T189,T68	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T53,*T87	Yes	T5,T53,T87	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T154,T155,T76	Yes	T154,T155,T76	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T76,T78,T153	Yes	T76,T78,T153	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T76,T78,T153	Yes	T76,T78,T153	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T154,T155,T76	Yes	T154,T155,T76	OUTPUT
cio_rx_i	Yes	Yes	T18,T19,T20	Yes	T4,T6,T18	INPUT
cio_tx_o	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T87,T293,T114	Yes	T87,T293,T114	OUTPUT
intr_tx_empty_o	Yes	Yes	T87,T293,T114	Yes	T87,T293,T114	OUTPUT
intr_rx_watermark_o	Yes	Yes	T87,T293,T114	Yes	T87,T293,T114	OUTPUT
intr_tx_done_o	Yes	Yes	T87,T325,T293	Yes	T87,T325,T293	OUTPUT
intr_rx_overflow_o	Yes	Yes	T87,T325,T293	Yes	T87,T325,T293	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	INPUT
tl_i.a_valid	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	INPUT
tl_o.a_ready	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
tl_o.d_error	Yes	Yes	T70,T73,T74	Yes	T68,T73,T146	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
tl_o.d_sink	Yes	Yes	T70,T73,T122	Yes	T68,T73,T122	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T5,*T189,*T73	Yes	T5,T189,T68	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T73,T122	Yes	T68,T70,T73	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T80,*T293	Yes	T5,T80,T293	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T154,T155,T76	Yes	T154,T155,T76	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T76,T78,T153	Yes	T78,T153,T360	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T78,T153,T360	Yes	T76,T78,T153	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T154,T155,T76	Yes	T154,T155,T76	OUTPUT
cio_rx_i	Yes	Yes	T80,T203,T340	Yes	T80,T203,T26	INPUT
cio_tx_o	Yes	Yes	T80,T203,T340	Yes	T80,T203,T340	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
intr_rx_watermark_o	Yes	Yes	T80,T293,T310	Yes	T80,T293,T310	OUTPUT
intr_tx_done_o	Yes	Yes	T80,T293,T310	Yes	T80,T293,T310	OUTPUT
intr_rx_overflow_o	Yes	Yes	T80,T293,T310	Yes	T80,T293,T310	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T293,T142	Yes	T5,T293,T142	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T293,T142	Yes	T5,T293,T142	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	INPUT
tl_i.a_valid	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_o.a_ready	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
tl_o.d_error	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T293,T142	Yes	T5,T293,T142	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T5,*T189,*T73	Yes	T5,T189,T68	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T70,T73,T122	Yes	T68,T73,T122	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T293,*T142	Yes	T5,T293,T142	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T154,T155,T76	Yes	T154,T155,T76	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T76,T78,T153	Yes	T76,T78,T153	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T76,T78,T153	Yes	T76,T78,T153	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T154,T155,T76	Yes	T154,T155,T76	OUTPUT
cio_rx_i	Yes	Yes	T142,T143,T326	Yes	T142,T143,T326	INPUT
cio_tx_o	Yes	Yes	T5,T142,T143	Yes	T5,T142,T143	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T5,T293,T142	Yes	T5,T293,T142	OUTPUT
intr_tx_empty_o	Yes	Yes	T293,T142,T310	Yes	T293,T142,T310	OUTPUT
intr_rx_watermark_o	Yes	Yes	T293,T142,T310	Yes	T293,T142,T310	OUTPUT
intr_tx_done_o	Yes	Yes	T293,T142,T310	Yes	T293,T142,T310	OUTPUT
intr_rx_overflow_o	Yes	Yes	T293,T142,T310	Yes	T293,T142,T310	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	INPUT
tl_i.a_valid	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_o.a_ready	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
tl_o.d_error	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
tl_o.d_sink	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T5,*T189,*T73	Yes	T5,T189,T68	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T5,*T293,*T310	Yes	T5,T293,T310	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T76,T78,T361	Yes	T76,T78,T153	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T76,T78,T153	Yes	T76,T78,T361	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T5,T154,T155	Yes	T5,T154,T155	OUTPUT
cio_rx_i	Yes	Yes	T28,T29,T342	Yes	T28,T29,T342	INPUT
cio_tx_o	Yes	Yes	T5,T28,T29	Yes	T5,T28,T29	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T293,T310,T28	Yes	T293,T310,T28	OUTPUT
intr_tx_empty_o	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
intr_rx_watermark_o	Yes	Yes	T293,T310,T28	Yes	T293,T310,T28	OUTPUT
intr_tx_done_o	Yes	Yes	T293,T310,T28	Yes	T293,T310,T28	OUTPUT
intr_rx_overflow_o	Yes	Yes	T293,T310,T28	Yes	T293,T310,T28	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_break_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_timeout_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T293,T310,T315	Yes	T293,T310,T315	OUTPUT

*Tests covering at least one bit in the range