Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T69,T70,T73	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T68,T73,T237	Yes	T68,T73,T237	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T19,T61,T207	Yes	T19,T61,T207	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T19,T61,T207	Yes	T19,T61,T207	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T5,T74,T147	Yes	T5,T122,T74	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T5,T68,T69	Yes	T5,T68,T69	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T19,T83,T61	Yes	T19,T83,T61	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T5,T1,T63	Yes	T5,T1,T63	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T5,T1,T63	Yes	T5,T1,T63	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T5,T1,T63	Yes	T5,T1,T63	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T5,T1,T63	Yes	T5,T1,T63	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T1,T63	Yes	T5,T1,T63	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T5,T1,T63	Yes	T5,T1,T63	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T5,*T1,*T63	Yes	T5,T1,T63	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T5,T1,T63	Yes	T5,T1,T63	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T73,T122	Yes	T1,T73,T122	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T1,T73,T122	Yes	T1,T73,T122	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T1,T68,T70	Yes	T1,T68,T70	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T1,T69,T70	Yes	T1,T68,T69	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T1,T68,T70	Yes	T1,T73,T122	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T73,T74	Yes	T1,T70,T73	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T1,T73,T122	Yes	T1,T70,T73	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T1,T73,T74	Yes	T1,T68,T73	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T68,T73,T74	Yes	T68,T73,T122	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T1,*T68,*T73	Yes	T1,T73,T122	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T71,T241	Yes	T1,T71,T241	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T71,T241	Yes	T1,T71,T241	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T71,T241	Yes	T1,T71,T241	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T1,T71,T241	Yes	T1,T71,T241	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T1,T71,T241	Yes	T1,T71,T241	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T71,*T241,*T242	Yes	T71,T241,T242	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T1,T71,T241	Yes	T1,T71,T241	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T19	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T71,T241,T242	Yes	T71,T241,T242	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T71,T241	Yes	T1,T71,T241	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T18,T19	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T71,*T241,*T242	Yes	T71,T241,T242	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T18,T19	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T1,T71,T241	Yes	T1,T71,T241	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T20,T53,T183	Yes	T20,T53,T183	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T1,T56,T57	Yes	T1,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T400,T56	Yes	T1,T400,T56	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T400,T56	Yes	T1,T400,T56	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T1,T56,T57	Yes	T1,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T1,T400,T56	Yes	T1,T400,T56	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T1,*T68,*T73	Yes	T1,T68,T73	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T73,T122,T146	Yes	T73,T122,T146	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T1,T400,T56	Yes	T1,T400,T56	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T1,T400,T56	Yes	T1,T400,T56	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T401,T253,T91	Yes	T401,T253,T91	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T68,T73	Yes	T1,T56,T57	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T1,T401,T253	Yes	T1,T56,T401	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T73,T146,T379	Yes	T73,T122,T146	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T1,*T73,*T146	Yes	T1,T68,T73	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T73,T122,T146	Yes	T73,T122,T146	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T1,*T400,*T275	Yes	T1,T400,T401	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T1,T400,T56	Yes	T1,T400,T56	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T19,T352,T343	Yes	T19,T352,T343	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	T5,*T1,*T72	Yes	T5,T1,T71	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T24,T187,T68	Yes	T24,T187,T68	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T73	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T24,T25,T150	Yes	T24,T25,T150	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T24,T25,T150	Yes	T24,T25,T150	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T73	Yes	T68,T69,T70	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T24,*T25,*T150	Yes	T24,T25,T150	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T154,T155,T24	Yes	T154,T155,T24	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T68,*T73,*T122	Yes	T68,T73,T122	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T68,T73,T146	Yes	T68,T70,T73	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T150,T151,T45	Yes	T150,T151,T45	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T150,T151,T45	Yes	T56,T150,T57	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T150,T151,T45	Yes	T150,T151,T45	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T68,T73,T146	Yes	T68,T70,T73	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T73,*T146,*T379	Yes	T68,T73,T122	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T150,*T151,*T45	Yes	T150,T151,T45	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T56,T150,T57	Yes	T56,T150,T57	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T5,*T189,*T68	Yes	T5,T189,T68	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T73,T122,T74	Yes	T73,T122,T74	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T70,T73,T74	Yes	T70,T73,T74	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	INPUT
tl_usbdev_i.d_error	Yes	Yes	T73,T122,T74	Yes	T73,T74,T146	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T5,*T189,*T73	Yes	T5,T189,T68	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T73,T122,T74	Yes	T73,T74,T146	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T5,*T293,*T310	Yes	T5,T293,T310	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T19	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T18,T19,T20	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T73	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T69,*T73,*T146	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T73	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T69,T70,T73	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T70,T73,T146	Yes	T70,T73,T122	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T70,T73,T122	Yes	T68,T70,T73	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T70,*T73,*T122	Yes	T70,T73,T146	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T19	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T69,T73,T122	Yes	T69,T73,T122	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T314,T641,T333	Yes	T314,T641,T333	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_hmac_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T73	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_hmac_i.d_sink	Yes	Yes	T69,T73,T122	Yes	T68,T69,T73	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T69,*T73,*T146	Yes	T68,T69,T70	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T69,T73,T122	Yes	T69,T73,T122	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T53,*T54,*T55	Yes	T53,T54,T55	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T1,*T68,*T70	Yes	T1,T68,T70	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T81,T421,T306	Yes	T81,T421,T306	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	INPUT
tl_kmac_i.d_error	Yes	Yes	T68,T70,T73	Yes	T73,T122,T74	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T81,T82,T421	Yes	T81,T421,T1	INPUT
tl_kmac_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T1,*T73,*T122	Yes	T1,T68,T70	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T421	Yes	T81,T421,T1	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T81,T82,T421	Yes	T81,T82,T421	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T355,T109,T285	Yes	T355,T109,T285	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T355,T109,T285	Yes	T355,T109,T285	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T85,T355,T109	Yes	T85,T355,T109	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T355,T109,T285	Yes	T355,T109,T285	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T85,T355,T109	Yes	T85,T355,T109	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T68,*T70,*T73	Yes	T68,T70,T73	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T85,T355,T109	Yes	T85,T355,T109	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T85,T355,T109	Yes	T85,T355,T109	INPUT
tl_aes_i.d_error	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T85,T355,T109	Yes	T85,T355,T109	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T85,T355,T109	Yes	T85,T355,T109	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T85,T355,T109	Yes	T85,T355,T109	INPUT
tl_aes_i.d_sink	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T146	Yes	T70,T73,T122	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T85,*T355,*T109	Yes	T85,T355,T109	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T85,T355,T109	Yes	T85,T355,T109	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T68,*T73,*T146	Yes	T68,T73,T146	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T73,T146,T147	Yes	T73,T146,T147	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T4,T6,T18	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T4,T6,T18	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T68,*T73,*T122	Yes	T68,T73,T122	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T82,*T85,*T121	Yes	T82,T53,T85	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T82,T85,T176	Yes	T82,T85,T176	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T73	Yes	T68,T69,T73	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_csrng_i.d_error	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T82,T85,T176	Yes	T82,T85,T176	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T4,T6,T18	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T4,T6,T18	INPUT
tl_csrng_i.d_sink	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T69,*T73,*T74	Yes	T68,T69,T73	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T82,*T85,*T176	Yes	T82,T85,T176	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T68,*T70,*T73	Yes	T68,T70,T73	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T68,T73,T74	Yes	T68,T73,T74	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_edn0_i.d_error	Yes	Yes	T68,T122,T74	Yes	T68,T122,T74	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T20	Yes	T4,T6,T18	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T4,T6,T18	INPUT
tl_edn0_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T68,*T73,*T122	Yes	T68,T70,T73	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T74	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T82,*T85,*T121	Yes	T82,T85,T121	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T70	Yes	T68,T69,T70	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	INPUT
tl_edn1_i.d_error	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	INPUT
tl_edn1_i.d_sink	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T69,*T73,*T146	Yes	T68,T69,T70	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T82,*T85,*T121	Yes	T82,T85,T121	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T82,T85,T121	Yes	T82,T85,T121	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T68,*T73,*T122	Yes	T68,T73,T122	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T73,*T122,*T74	Yes	T68,T73,T122	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T73,T122,T74	Yes	T70,T73,T122	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T6,*T19,*T80	Yes	T6,T19,T80	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T6,T19,T80	Yes	T6,T19,T80	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T53,T85,T54	Yes	T53,T85,T54	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T1,*T72,*T188	Yes	T1,T72,T188	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	INPUT
tl_otbn_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T73	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	INPUT
tl_otbn_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T1,*T72,*T188	Yes	T1,T72,T188	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T53,*T85,*T1	Yes	T53,T85,T1	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T53,T85,T1	Yes	T53,T85,T1	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T68,*T70,*T73	Yes	T68,T70,T73	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T73,T146,T147	Yes	T73,T146,T147	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T68,T73,T146	Yes	T68,T73,T146	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	INPUT
tl_keymgr_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T82,T208,T209	Yes	T82,T208,T209	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T68,*T73,*T146	Yes	T68,T70,T73	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T68,T73,T146	Yes	T68,T73,T74	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T82,*T53,*T208	Yes	T82,T53,T208	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T82,T53,T208	Yes	T82,T53,T208	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T1,*T68,*T69	Yes	T1,T68,T69	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T1,T69,T70	Yes	T1,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T1,*T69,*T70	Yes	T1,T68,T69	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T71,*T242,*T68	Yes	T71,T242,T68	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T122,T146,T147	Yes	T122,T146,T147	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T171,T287,T288	Yes	T171,T287,T288	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T171,T111	Yes	T53,T54,T55	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T110,T171,T111	Yes	T53,T54,T55	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T73,*T122,*T146	Yes	T71,T242,T68	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T110,*T171,*T111	Yes	T110,T171,T111	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T19	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range