Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_peri_ni	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_main_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	INPUT
tl_main_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_main_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_error	Yes	Yes	T19,T352,T343	Yes	T19,T352,T343	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	T5,*T1,*T72	Yes	T5,T1,T71	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	INPUT
tl_uart0_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T5,T87,T293	Yes	T5,T87,T293	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	INPUT
tl_uart0_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T5,*T189,*T68	Yes	T5,T189,T68	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T5,*T53,*T87	Yes	T5,T53,T87	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T5,T53,T87	Yes	T5,T53,T87	INPUT
tl_uart1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	INPUT
tl_uart1_i.d_error	Yes	Yes	T70,T73,T74	Yes	T68,T73,T146	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	INPUT
tl_uart1_i.d_sink	Yes	Yes	T70,T73,T122	Yes	T68,T73,T122	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T5,*T189,*T73	Yes	T5,T189,T68	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T70,T73,T122	Yes	T68,T70,T73	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T5,*T80,*T293	Yes	T5,T80,T293	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T5,T80,T293	Yes	T5,T80,T293	INPUT
tl_uart2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T5,T293,T142	Yes	T5,T293,T142	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T5,T293,T142	Yes	T5,T293,T142	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_uart2_i.d_error	Yes	Yes	T70,T73,T122	Yes	T70,T73,T122	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T5,T293,T142	Yes	T5,T293,T142	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_uart2_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T5,*T189,*T73	Yes	T5,T189,T68	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T70,T73,T122	Yes	T68,T73,T122	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T5,*T293,*T142	Yes	T5,T293,T142	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_uart3_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_uart3_i.d_error	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T5,T293,T310	Yes	T5,T293,T310	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_uart3_i.d_sink	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T5,*T189,*T73	Yes	T5,T189,T68	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T5,*T293,*T310	Yes	T5,T293,T310	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T5,T293,T154	Yes	T5,T293,T154	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T201,T202,T376	Yes	T201,T202,T376	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T201,T202,T376	Yes	T201,T202,T376	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T154,T155,T56	Yes	T154,T155,T56	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T154,T155,T56	Yes	T154,T155,T56	INPUT
tl_i2c0_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T201,T202,T311	Yes	T201,T202,T311	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T154,T155,T77	Yes	T154,T155,T56	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T154,T155,T77	Yes	T154,T155,T56	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T68,*T70,*T73	Yes	T68,T70,T73	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T201,*T202,*T376	Yes	T201,T202,T376	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T154,T155,T56	Yes	T154,T155,T56	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T204,T96,T97	Yes	T204,T96,T97	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T204,T96,T97	Yes	T204,T96,T97	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T154,T155,T204	Yes	T154,T155,T204	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T154,T155,T204	Yes	T154,T155,T204	INPUT
tl_i2c1_i.d_error	Yes	Yes	T73,T122,T146	Yes	T68,T73,T122	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T204,T96,T97	Yes	T204,T96,T97	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T154,T155,T204	Yes	T154,T155,T204	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T154,T155,T204	Yes	T154,T155,T204	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T73,*T122,*T146	Yes	T68,T70,T73	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T204,*T96,*T97	Yes	T204,T96,T97	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T154,T155,T204	Yes	T154,T155,T204	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T322,T376,T323	Yes	T322,T376,T323	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T322,T376,T323	Yes	T322,T376,T323	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T154,T155,T322	Yes	T154,T155,T322	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T154,T155,T322	Yes	T154,T155,T322	INPUT
tl_i2c2_i.d_error	Yes	Yes	T73,T122,T146	Yes	T73,T122,T74	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T322,T323,T327	Yes	T322,T323,T327	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T154,T155,T322	Yes	T154,T155,T322	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T154,T155,T322	Yes	T154,T155,T322	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T73,T122,T74	Yes	T68,T73,T122	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T73,*T146,*T379	Yes	T68,T73,T122	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T73,T122,T146	Yes	T68,T73,T122	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T322,*T376,*T323	Yes	T322,T376,T323	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T154,T155,T322	Yes	T154,T155,T322	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T1,T150,T151	Yes	T1,T150,T151	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T1,T150,T151	Yes	T1,T150,T151	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T1,T56,T150	Yes	T1,T56,T150	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T1,T56,T150	Yes	T1,T56,T150	INPUT
tl_pattgen_i.d_error	Yes	Yes	T68,T70,T122	Yes	T68,T122,T146	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T1,T150,T151	Yes	T1,T150,T151	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T150,T151	Yes	T1,T56,T150	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T1,T150,T151	Yes	T1,T56,T150	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T1,T68,T73	Yes	T1,T68,T70	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T1,*T150,*T151	Yes	T1,T150,T151	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T1,T56,T150	Yes	T1,T56,T150	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T1,*T73,*T146	Yes	T1,T68,T70	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T144,*T1,*T205	Yes	T144,T1,T205	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T144,T1,T205	Yes	T144,T1,T205	INPUT
tl_gpio_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_gpio_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T27,T38,T39	Yes	T27,T38,T39	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T27,T38,T39	Yes	T144,T27,T56	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T27,T38,T39	Yes	T144,T27,T56	INPUT
tl_gpio_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T68,*T70,*T73	Yes	T68,T70,T73	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T18,*T19,*T82	Yes	T4,T6,T18	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T138,T24,T25	Yes	T138,T24,T25	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T138,T24,T25	Yes	T138,T24,T25	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T138,T24,T56	Yes	T138,T24,T56	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T138,T24,T56	Yes	T138,T24,T56	INPUT
tl_spi_device_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T73,T74	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T138,T24,T25	Yes	T138,T24,T25	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T138,T24,T25	Yes	T138,T24,T25	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T138,T24,T56	Yes	T138,T24,T25	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T68,*T70,*T73	Yes	T68,T73,T122	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T138,*T24,*T56	Yes	T138,T24,T25	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T138,T24,T56	Yes	T138,T24,T56	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T88,T144,T240	Yes	T88,T144,T240	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T88,T144,T240	Yes	T88,T144,T240	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T88,T144,T240	Yes	T88,T144,T240	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T88,T144,T240	Yes	T88,T144,T240	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T68,T73,T74	Yes	T68,T73,T146	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T88,T240,T292	Yes	T88,T240,T292	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T88,T144,T240	Yes	T88,T144,T240	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T88,T144,T240	Yes	T88,T144,T240	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T68,T73,T146	Yes	T68,T73,T74	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T146	Yes	T68,T70,T73	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T68,T73,T74	Yes	T68,T73,T146	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T88,*T144,*T240	Yes	T88,T144,T240	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T88,T144,T240	Yes	T88,T144,T240	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T83,T75	Yes	T6,T83,T75	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T6,T83,T75	Yes	T6,T83,T75	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T6,T83,T75	Yes	T6,T83,T75	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T6,T83,T75	Yes	T6,T83,T75	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T70,T73,T122	Yes	T68,T70,T73	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T83,T75	Yes	T6,T83,T75	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T83,T75	Yes	T6,T83,T75	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T6,T83,T75	Yes	T6,T83,T75	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T70,T73,T122	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T1,*T68,*T70	Yes	T1,T68,T70	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T70,T73,T122	Yes	T68,T70,T73	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T6,*T83,*T75	Yes	T6,T83,T75	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T6,T83,T75	Yes	T6,T83,T75	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T69,T70,T73	Yes	T69,T73,T122	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T82	Yes	T4,T6,T18	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T18,T19,T82	Yes	T4,T6,T18	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T69,T73,T122	Yes	T68,T69,T70	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T1,*T69,*T73	Yes	T1,T68,T69	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T69,T73,T122	Yes	T68,T69,T73	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T80,T87,T113	Yes	T80,T87,T113	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T80,T87,T107	Yes	T80,T87,T107	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T73,T122,T74	Yes	T73,T122,T74	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T80,T87,T113	Yes	T80,T87,T113	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T19,T80	Yes	T4,T6,T18	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T18,T19,T80	Yes	T4,T6,T18	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T146	Yes	T68,T73,T122	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T80,*T87,*T113	Yes	T80,T87,T113	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T1,*T73,*T74	Yes	T1,T68,T70	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T73,T146,T147	Yes	T73,T146,T147	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T1,*T148,*T149	Yes	T1,T148,T149	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T68,T73,T74	Yes	T68,T73,T146	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T20,*T82	Yes	T4,T20,T82	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T19	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T18,T19	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T1,T68,T70	Yes	T1,T68,T70	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T5,T18,T19	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T1,T68,T70	Yes	T1,T68,T70	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T4,T18,T80	Yes	T4,T18,T80	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T4,T18,T80	Yes	T4,T18,T80	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T4,T18,T80	Yes	T4,T18,T80	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T4,T18,T80	Yes	T4,T18,T80	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T4,T18,T20	Yes	T4,T18,T20	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T60,T112	Yes	T18,T60,T112	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T4,T18,T53	Yes	T4,T18,T80	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T1,*T289,*T290	Yes	T1,T289,T290	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T18,*T20,*T60	Yes	T4,T18,T80	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T4,T18,T80	Yes	T4,T18,T80	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T53,T90,T123	Yes	T53,T90,T123	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T90,T123	Yes	T53,T90,T123	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T18,T19,T20	Yes	T4,T6,T18	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T73,*T74,*T146	Yes	T68,T73,T74	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T73,T74	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T18,*T19,*T20	Yes	T4,T6,T18	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T73	Yes	T68,T69,T70	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T69,T70,T73	Yes	T68,T69,T70	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T6,*T19,*T75	Yes	T6,T19,T75	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T6,T19,T75	Yes	T6,T19,T75	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T68,T73,T122	Yes	T68,T73,T122	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T110,T169,T111	Yes	T110,T169,T111	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T110,T169,T111	Yes	T53,T54,T55	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T110,T169,T111	Yes	T53,T54,T55	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T68,*T73,*T146	Yes	T68,T70,T73	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T110,*T169,*T111	Yes	T110,T169,T111	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T53,T54,T55	Yes	T53,T54,T55	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T6,T19,T82	Yes	T6,T19,T82	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T18,T19	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T6,T19,T82	Yes	T6,T19,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T18	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T6,T19,T82	Yes	T6,T19,T82	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T69,T70,T73	Yes	T69,T70,T73	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T72,*T188,*T190	Yes	T72,T188,T190	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T18	Yes	T4,T6,T18	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T4,T6,T18	Yes	T4,T6,T18	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T6,T19,T83	Yes	T6,T19,T83	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T6,T19,T83	Yes	T6,T19,T83	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T6,T19,T83	Yes	T6,T19,T83	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T6,T19,T83	Yes	T6,T19,T83	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T6,T19,T83	Yes	T6,T19,T83	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T19,T83	Yes	T6,T19,T83	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T6,T19,T83	Yes	T6,T19,T83	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T69,*T70,*T73	Yes	T71,T241,T242	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T6,*T19,*T83	Yes	T6,T19,T83	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T6,T19,T83	Yes	T6,T19,T83	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T293,T47	Yes	T5,T293,T47	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T5,T293,T47	Yes	T5,T293,T47	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T5,T293,T47	Yes	T5,T293,T47	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T5,T293,T47	Yes	T5,T293,T47	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T73,T122,T146	Yes	T73,T122,T146	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T293,T47	Yes	T5,T293,T47	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T293,T47	Yes	T5,T293,T47	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T47,T177	Yes	T5,T293,T47	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T68,T70,T73	Yes	T70,T73,T122	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T5,*T189,*T73	Yes	T5,T189,T68	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T68,T70,T73	Yes	T68,T70,T73	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T293,*T47	Yes	T5,T293,T47	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T5,T293,T47	Yes	T5,T293,T47	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T99,T100,T101	Yes	T99,T100,T101	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T99,T56,T100	Yes	T99,T56,T100	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T99,T56,T100	Yes	T99,T56,T100	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T99,T101,T102	Yes	T99,T101,T7	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T99,T100,T101	Yes	T99,T56,T100	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T99,T100,T101	Yes	T99,T56,T100	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T68,T69,T73	Yes	T68,T69,T73	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T69,*T73,*T122	Yes	T68,T69,T70	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T69,T70,T73	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T99,*T100,*T101	Yes	T99,T100,T101	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T99,T56,T100	Yes	T99,T56,T100	INPUT
tl_ast_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	T5,*T1,*T71	Yes	T5,T1,T71	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T68,T69,T70	Yes	T68,T69,T70	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T5,T1,T72	Yes	T5,T1,T72	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_ast_i.d_error	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T68,T70,T73	Yes	T68,T73,T122	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T5,T18,T19	Yes	T4,T5,T6	INPUT
tl_ast_i.d_sink	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	T68,T73,*T74	Yes	T68,T73,T122	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T68,T73,T122	Yes	T68,T70,T73	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T68,*T70,*T73	Yes	T68,T73,T122	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range