Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T170,T282
0	1	Covered	T170,T282,T283
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T170,T282,T283
1	Covered	T1,T170,T282

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T170,T282,T283
1	Covered	T1,T170,T282

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T170,T282,T283
1	1	Covered	T170,T282,T283

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T170,T282
1	0	Covered	T170,T282,T283
1	1	Covered	T170,T282,T283

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T170,T282,T283

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T170,T282
0	Covered	T170,T282,T283

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T170,T282
0	Covered	T170,T282,T283

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	920509570	905937606	0	0
CheckNGreaterZero_A	1954	1954	0	0
GntImpliesReady_A	920509570	8375	0	0
GntImpliesValid_A	920509570	8375	0	0
GrantKnown_A	920509570	905937606	0	0
IdxKnown_A	920509570	905937606	0	0
IndexIsCorrect_A	920509570	8375	0	0
NoReadyValidNoGrant_A	920509570	0	0	0
Priority_A	920509570	8375	0	0
ReadyAndValidImplyGrant_A	920509570	8375	0	0
ReqAndReadyImplyGrant_A	920509570	8375	0	0
ReqImpliesValid_A	920509570	8375	0	0
ValidKnown_A	920509570	905937606	0	0
gen_data_port_assertion.DataFlow_A	920509570	8375	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	905937606	0	0
T4	213316	213200	0	0
T5	416280	0	0	0
T6	309932	309808	0	0
T18	877218	876518	0	0
T19	493670	493438	0	0
T20	795722	795688	0	0
T75	0	315958	0	0
T80	363576	363460	0	0
T81	146594	146492	0	0
T82	1518846	1518626	0	0
T83	523536	523200	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1954	1954	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T80	2	2	0	0
T81	2	2	0	0
T82	2	2	0	0
T83	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	8375	0	0
T27	408364	0	0	0
T156	275734	0	0	0
T170	173250	2797	0	0
T209	510168	0	0	0
T212	492168	0	0	0
T232	511660	0	0	0
T270	469626	0	0	0
T282	0	2787	0	0
T283	0	2791	0	0
T284	308902	0	0	0
T285	155382	0	0	0
T286	180110	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	8375	0	0
T27	408364	0	0	0
T156	275734	0	0	0
T170	173250	2797	0	0
T209	510168	0	0	0
T212	492168	0	0	0
T232	511660	0	0	0
T270	469626	0	0	0
T282	0	2787	0	0
T283	0	2791	0	0
T284	308902	0	0	0
T285	155382	0	0	0
T286	180110	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	905937606	0	0
T4	213316	213200	0	0
T5	416280	0	0	0
T6	309932	309808	0	0
T18	877218	876518	0	0
T19	493670	493438	0	0
T20	795722	795688	0	0
T75	0	315958	0	0
T80	363576	363460	0	0
T81	146594	146492	0	0
T82	1518846	1518626	0	0
T83	523536	523200	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	905937606	0	0
T4	213316	213200	0	0
T5	416280	0	0	0
T6	309932	309808	0	0
T18	877218	876518	0	0
T19	493670	493438	0	0
T20	795722	795688	0	0
T75	0	315958	0	0
T80	363576	363460	0	0
T81	146594	146492	0	0
T82	1518846	1518626	0	0
T83	523536	523200	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	8375	0	0
T27	408364	0	0	0
T156	275734	0	0	0
T170	173250	2797	0	0
T209	510168	0	0	0
T212	492168	0	0	0
T232	511660	0	0	0
T270	469626	0	0	0
T282	0	2787	0	0
T283	0	2791	0	0
T284	308902	0	0	0
T285	155382	0	0	0
T286	180110	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	8375	0	0
T27	408364	0	0	0
T156	275734	0	0	0
T170	173250	2797	0	0
T209	510168	0	0	0
T212	492168	0	0	0
T232	511660	0	0	0
T270	469626	0	0	0
T282	0	2787	0	0
T283	0	2791	0	0
T284	308902	0	0	0
T285	155382	0	0	0
T286	180110	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	8375	0	0
T27	408364	0	0	0
T156	275734	0	0	0
T170	173250	2797	0	0
T209	510168	0	0	0
T212	492168	0	0	0
T232	511660	0	0	0
T270	469626	0	0	0
T282	0	2787	0	0
T283	0	2791	0	0
T284	308902	0	0	0
T285	155382	0	0	0
T286	180110	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	8375	0	0
T27	408364	0	0	0
T156	275734	0	0	0
T170	173250	2797	0	0
T209	510168	0	0	0
T212	492168	0	0	0
T232	511660	0	0	0
T270	469626	0	0	0
T282	0	2787	0	0
T283	0	2791	0	0
T284	308902	0	0	0
T285	155382	0	0	0
T286	180110	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	8375	0	0
T27	408364	0	0	0
T156	275734	0	0	0
T170	173250	2797	0	0
T209	510168	0	0	0
T212	492168	0	0	0
T232	511660	0	0	0
T270	469626	0	0	0
T282	0	2787	0	0
T283	0	2791	0	0
T284	308902	0	0	0
T285	155382	0	0	0
T286	180110	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	905937606	0	0
T4	213316	213200	0	0
T5	416280	0	0	0
T6	309932	309808	0	0
T18	877218	876518	0	0
T19	493670	493438	0	0
T20	795722	795688	0	0
T75	0	315958	0	0
T80	363576	363460	0	0
T81	146594	146492	0	0
T82	1518846	1518626	0	0
T83	523536	523200	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	920509570	8375	0	0
T27	408364	0	0	0
T156	275734	0	0	0
T170	173250	2797	0	0
T209	510168	0	0	0
T212	492168	0	0	0
T232	511660	0	0	0
T270	469626	0	0	0
T282	0	2787	0	0
T283	0	2791	0	0
T284	308902	0	0	0
T285	155382	0	0	0
T286	180110	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T170,T282
0	1	Covered	T170,T282,T283
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T170,T282,T283
1	Covered	T1,T170,T282

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T170,T282,T283
1	Covered	T1,T170,T282

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T170,T282,T283
1	1	Covered	T170,T282,T283

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T170,T282
1	0	Covered	T170,T282,T283
1	1	Covered	T170,T282,T283

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T170,T282,T283

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T170,T282
0	Covered	T170,T282,T283

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T170,T282
0	Covered	T170,T282,T283

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	460254785	452968803	0	0
CheckNGreaterZero_A	977	977	0	0
GntImpliesReady_A	460254785	5188	0	0
GntImpliesValid_A	460254785	5188	0	0
GrantKnown_A	460254785	452968803	0	0
IdxKnown_A	460254785	452968803	0	0
IndexIsCorrect_A	460254785	5188	0	0
NoReadyValidNoGrant_A	460254785	0	0	0
Priority_A	460254785	5188	0	0
ReadyAndValidImplyGrant_A	460254785	5188	0	0
ReqAndReadyImplyGrant_A	460254785	5188	0	0
ReqImpliesValid_A	460254785	5188	0	0
ValidKnown_A	460254785	452968803	0	0
gen_data_port_assertion.DataFlow_A	460254785	5188	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	452968803	0	0
T4	106658	106600	0	0
T5	208140	0	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T75	0	157979	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977	977	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	5188	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1734	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1726	0	0
T283	0	1728	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	5188	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1734	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1726	0	0
T283	0	1728	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	452968803	0	0
T4	106658	106600	0	0
T5	208140	0	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T75	0	157979	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	452968803	0	0
T4	106658	106600	0	0
T5	208140	0	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T75	0	157979	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	5188	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1734	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1726	0	0
T283	0	1728	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	5188	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1734	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1726	0	0
T283	0	1728	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	5188	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1734	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1726	0	0
T283	0	1728	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	5188	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1734	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1726	0	0
T283	0	1728	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	5188	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1734	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1726	0	0
T283	0	1728	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	452968803	0	0
T4	106658	106600	0	0
T5	208140	0	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T75	0	157979	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	5188	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1734	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1726	0	0
T283	0	1728	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T170,T282
0	1	Covered	T170,T282,T283
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T170,T282,T283
1	Covered	T1,T170,T282

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T170,T282,T283
1	Covered	T1,T170,T282

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T170,T282,T283
1	1	Covered	T170,T282,T283

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T170,T282
1	0	Covered	T170,T282,T283
1	1	Covered	T170,T282,T283

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T170,T282,T283

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T170,T282
0	Covered	T170,T282,T283

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T170,T282
0	Covered	T170,T282,T283

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	460254785	452968803	0	0
CheckNGreaterZero_A	977	977	0	0
GntImpliesReady_A	460254785	3187	0	0
GntImpliesValid_A	460254785	3187	0	0
GrantKnown_A	460254785	452968803	0	0
IdxKnown_A	460254785	452968803	0	0
IndexIsCorrect_A	460254785	3187	0	0
NoReadyValidNoGrant_A	460254785	0	0	0
Priority_A	460254785	3187	0	0
ReadyAndValidImplyGrant_A	460254785	3187	0	0
ReqAndReadyImplyGrant_A	460254785	3187	0	0
ReqImpliesValid_A	460254785	3187	0	0
ValidKnown_A	460254785	452968803	0	0
gen_data_port_assertion.DataFlow_A	460254785	3187	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	452968803	0	0
T4	106658	106600	0	0
T5	208140	0	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T75	0	157979	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	977	977	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0
T82	1	1	0	0
T83	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	3187	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1063	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1061	0	0
T283	0	1063	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	3187	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1063	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1061	0	0
T283	0	1063	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	452968803	0	0
T4	106658	106600	0	0
T5	208140	0	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T75	0	157979	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	452968803	0	0
T4	106658	106600	0	0
T5	208140	0	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T75	0	157979	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	3187	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1063	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1061	0	0
T283	0	1063	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	3187	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1063	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1061	0	0
T283	0	1063	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	3187	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1063	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1061	0	0
T283	0	1063	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	3187	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1063	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1061	0	0
T283	0	1063	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	3187	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1063	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1061	0	0
T283	0	1063	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	452968803	0	0
T4	106658	106600	0	0
T5	208140	0	0	0
T6	154966	154904	0	0
T18	438609	438259	0	0
T19	246835	246719	0	0
T20	397861	397844	0	0
T75	0	157979	0	0
T80	181788	181730	0	0
T81	73297	73246	0	0
T82	759423	759313	0	0
T83	261768	261600	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	460254785	3187	0	0
T27	204182	0	0	0
T156	137867	0	0	0
T170	86625	1063	0	0
T209	255084	0	0	0
T212	246084	0	0	0
T232	255830	0	0	0
T270	234813	0	0	0
T282	0	1061	0	0
T283	0	1063	0	0
T284	154451	0	0	0
T285	77691	0	0	0
T286	90055	0	0	0