Unified Coverage Report :: Module :: prim_alert_sender

Module : prim_alert_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender	87.50			87.50
tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender	100.00			100.00
tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50			87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.83	96.47	89.29	99.75		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.93	98.96	82.38	98.84		77.45	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.93	99.65	100.00	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.83	96.47	89.29	99.75		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.83	96.47	89.29	99.75		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.83	96.47	89.29	99.75		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
alert_test_i	Yes	Yes	T53,T2,T181	Yes	T53,T2,T181	INPUT
alert_req_i	Yes	Yes	T80,T2,T215	Yes	T80,T2,T215	INPUT
alert_ack_o	Yes	Yes	T80,T2,T215	Yes	T80,T2,T215	OUTPUT
alert_state_o	Yes	Yes	T80,T2,T215	Yes	T80,T2,T215	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
alert_rx_i.ack_p	Yes	Yes	T53,T80,T2	Yes	T53,T80,T2	INPUT
alert_rx_i.ping_n	Yes	Yes	T150,T81,T82	Yes	T150,T81,T82	INPUT
alert_rx_i.ping_p	Yes	Yes	T150,T81,T82	Yes	T150,T81,T82	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T53,T80,T2	Yes	T53,T80,T2	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

	Total	Covered	Percent
Totals	12	10	83.33
Total Bits	24	21	87.50
Total Bits 0->1	12	11	91.67
Total Bits 1->0	12	10	83.33

Ports	12	10	83.33
Port Bits	24	21	87.50
Port Bits 0->1	12	11	91.67
Port Bits 1->0	12	10	83.33

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
alert_test_i	Yes	Yes	T2,T54,T55	Yes	T2,T54,T55	INPUT
alert_req_i	Yes	Yes	T377	Yes	T377	INPUT
alert_ack_o	No	No		No		OUTPUT
alert_state_o	No	No		Yes	T377	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
alert_rx_i.ack_p	Yes	Yes	T2,T82,T83	Yes	T2,T82,T83	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T2,T82,T83	Yes	T2,T82,T83	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_ni	Yes	Yes	T15,T38,T39	Yes	T4,T1,T5	INPUT
alert_test_i	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
alert_req_i	Yes	Yes	T80,T90,T91	Yes	T80,T90,T91	INPUT
alert_ack_o	Yes	Yes	T80,T90,T91	Yes	T80,T90,T91	OUTPUT
alert_state_o	Yes	Yes	T80,T90,T91	Yes	T80,T90,T91	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
alert_rx_i.ack_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
alert_rx_i.ping_n	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_rx_i.ping_p	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
alert_test_i	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
alert_req_i	Yes	Yes	T340,T350,T396	Yes	T340,T350,T395	INPUT
alert_ack_o	Yes	Yes	T340,T350,T395	Yes	T340,T350,T395	OUTPUT
alert_state_o	Yes	Yes	T340,T350,T396	Yes	T340,T350,T395	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
alert_rx_i.ack_p	Yes	Yes	T150,T340,T82	Yes	T150,T340,T82	INPUT
alert_rx_i.ping_n	Yes	Yes	T150,T82,T83	Yes	T150,T82,T83	INPUT
alert_rx_i.ping_p	Yes	Yes	T150,T82,T83	Yes	T150,T82,T83	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T150,T340,T82	Yes	T150,T340,T82	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
alert_test_i	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
alert_req_i	Yes	Yes	T655	Yes	T655	INPUT
alert_ack_o	Yes	Yes	T655	Yes	T655	OUTPUT
alert_state_o	Yes	Yes	T655	Yes	T655	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
alert_rx_i.ack_p	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
alert_test_i	Yes	Yes	T53,T2,T181	Yes	T53,T2,T181	INPUT
alert_req_i	Yes	Yes	T2	Yes	T2	INPUT
alert_ack_o	Yes	Yes	T2	Yes	T2	OUTPUT
alert_state_o	Yes	Yes	T2	Yes	T2	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
alert_rx_i.ack_p	Yes	Yes	T53,T2,T181	Yes	T53,T2,T181	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T53,T2,T181	Yes	T53,T2,T181	OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

	Total	Covered	Percent
Totals	12	12	100.00
Total Bits	24	24	100.00
Total Bits 0->1	12	12	100.00
Total Bits 1->0	12	12	100.00

Ports	12	12	100.00
Port Bits	24	24	100.00
Port Bits 0->1	12	12	100.00
Port Bits 1->0	12	12	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
rst_ni	Yes	Yes	T15,T59,T38	Yes	T4,T1,T5	INPUT
alert_test_i	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	INPUT
alert_req_i	Yes	Yes	T215,T236,T216	Yes	T215,T236,T216	INPUT
alert_ack_o	Yes	Yes	T215,T216,T218	Yes	T215,T216,T218	OUTPUT
alert_state_o	Yes	Yes	T215,T216,T218	Yes	T215,T236,T216	OUTPUT
alert_rx_i.ack_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	INPUT
alert_rx_i.ack_p	Yes	Yes	T215,T216,T218	Yes	T215,T216,T218	INPUT
alert_rx_i.ping_n	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_rx_i.ping_p	Yes	Yes	T82,T83,T148	Yes	T82,T83,T148	INPUT
alert_tx_o.alert_n	Yes	Yes	T4,T1,T5	Yes	T4,T1,T5	OUTPUT
alert_tx_o.alert_p	Yes	Yes	T215,T216,T218	Yes	T215,T236,T216	OUTPUT