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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.15 95.62 94.06 95.43 94.90 97.35 99.53


Total test records in report: 2871
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T1018 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3235044463 Jun 25 07:39:50 PM PDT 24 Jun 25 07:47:24 PM PDT 24 6962029976 ps
T1019 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2225748063 Jun 25 07:46:20 PM PDT 24 Jun 25 07:51:32 PM PDT 24 3511760166 ps
T1020 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1100745852 Jun 25 07:53:07 PM PDT 24 Jun 25 08:09:46 PM PDT 24 4931740642 ps
T219 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2366680751 Jun 25 07:39:37 PM PDT 24 Jun 25 07:54:42 PM PDT 24 6230160620 ps
T7 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2009728456 Jun 25 08:06:54 PM PDT 24 Jun 25 08:12:54 PM PDT 24 3527389268 ps
T1021 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1633179385 Jun 25 08:05:24 PM PDT 24 Jun 25 08:49:55 PM PDT 24 29081056976 ps
T54 /workspace/coverage/default/2.chip_sw_alert_test.3451852200 Jun 25 08:04:46 PM PDT 24 Jun 25 08:11:06 PM PDT 24 3207991868 ps
T19 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1666005298 Jun 25 07:39:33 PM PDT 24 Jun 25 07:43:49 PM PDT 24 2583527610 ps
T151 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1065466222 Jun 25 07:39:43 PM PDT 24 Jun 25 07:41:43 PM PDT 24 2783270847 ps
T766 /workspace/coverage/default/90.chip_sw_all_escalation_resets.1848613787 Jun 25 08:17:20 PM PDT 24 Jun 25 08:26:04 PM PDT 24 4065024440 ps
T200 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4233222226 Jun 25 07:42:04 PM PDT 24 Jun 25 07:46:27 PM PDT 24 3295902154 ps
T1022 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.4091081161 Jun 25 08:00:57 PM PDT 24 Jun 25 08:19:23 PM PDT 24 7586423784 ps
T693 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.424728942 Jun 25 08:12:48 PM PDT 24 Jun 25 08:18:51 PM PDT 24 3616164148 ps
T756 /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1130112865 Jun 25 08:13:28 PM PDT 24 Jun 25 08:20:33 PM PDT 24 3105612302 ps
T329 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3662063861 Jun 25 07:48:05 PM PDT 24 Jun 25 07:58:59 PM PDT 24 3929162730 ps
T1023 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.756238063 Jun 25 08:01:25 PM PDT 24 Jun 25 09:12:15 PM PDT 24 16024100599 ps
T1024 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.350261834 Jun 25 08:12:51 PM PDT 24 Jun 25 08:20:28 PM PDT 24 3773312318 ps
T1025 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2226178940 Jun 25 08:04:12 PM PDT 24 Jun 25 08:20:11 PM PDT 24 8464105386 ps
T1026 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.99872725 Jun 25 07:58:32 PM PDT 24 Jun 25 08:11:07 PM PDT 24 4191939648 ps
T314 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.13843059 Jun 25 08:01:12 PM PDT 24 Jun 25 08:27:38 PM PDT 24 10274579300 ps
T1027 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767251516 Jun 25 08:14:08 PM PDT 24 Jun 25 08:21:04 PM PDT 24 3846120900 ps
T1028 /workspace/coverage/default/2.chip_sw_power_idle_load.3934448618 Jun 25 08:07:57 PM PDT 24 Jun 25 08:19:39 PM PDT 24 3948882984 ps
T1029 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1357952760 Jun 25 08:05:59 PM PDT 24 Jun 25 08:16:56 PM PDT 24 3718327080 ps
T690 /workspace/coverage/default/83.chip_sw_all_escalation_resets.3887024247 Jun 25 08:16:59 PM PDT 24 Jun 25 08:26:21 PM PDT 24 4774898464 ps
T502 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1821452300 Jun 25 08:02:29 PM PDT 24 Jun 25 08:15:37 PM PDT 24 4944929076 ps
T291 /workspace/coverage/default/1.chip_sw_flash_init.3727931427 Jun 25 07:48:01 PM PDT 24 Jun 25 08:24:28 PM PDT 24 24950125980 ps
T1030 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3047760882 Jun 25 08:12:26 PM PDT 24 Jun 25 09:27:36 PM PDT 24 15418092296 ps
T683 /workspace/coverage/default/62.chip_sw_all_escalation_resets.546516311 Jun 25 08:14:52 PM PDT 24 Jun 25 08:25:49 PM PDT 24 6400440520 ps
T634 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1223941301 Jun 25 08:04:36 PM PDT 24 Jun 25 08:16:48 PM PDT 24 3553307916 ps
T762 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4103668439 Jun 25 08:17:08 PM PDT 24 Jun 25 08:23:56 PM PDT 24 4214868664 ps
T1031 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2915793858 Jun 25 08:03:19 PM PDT 24 Jun 25 08:31:24 PM PDT 24 6175325940 ps
T1032 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1320213816 Jun 25 07:39:36 PM PDT 24 Jun 25 07:47:37 PM PDT 24 4756811460 ps
T732 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749477365 Jun 25 08:10:11 PM PDT 24 Jun 25 08:16:41 PM PDT 24 4094507694 ps
T371 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.967818233 Jun 25 07:55:47 PM PDT 24 Jun 25 08:03:40 PM PDT 24 5793152720 ps
T395 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.860537600 Jun 25 08:15:35 PM PDT 24 Jun 25 08:21:36 PM PDT 24 3540734200 ps
T292 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.282007045 Jun 25 08:00:24 PM PDT 24 Jun 25 09:46:42 PM PDT 24 48602376372 ps
T1033 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1825955890 Jun 25 07:37:20 PM PDT 24 Jun 25 07:50:37 PM PDT 24 7789336832 ps
T1034 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1113664082 Jun 25 08:08:09 PM PDT 24 Jun 25 08:40:20 PM PDT 24 9233947162 ps
T1035 /workspace/coverage/default/2.chip_sw_kmac_idle.2343555070 Jun 25 08:03:41 PM PDT 24 Jun 25 08:08:05 PM PDT 24 3306269040 ps
T289 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.153109397 Jun 25 07:53:33 PM PDT 24 Jun 25 08:44:02 PM PDT 24 11852224512 ps
T1036 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3444927326 Jun 25 07:58:52 PM PDT 24 Jun 25 08:23:20 PM PDT 24 8854892410 ps
T220 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3162106502 Jun 25 08:09:23 PM PDT 24 Jun 25 08:19:08 PM PDT 24 6047026802 ps
T1037 /workspace/coverage/default/1.chip_sw_aes_masking_off.523137762 Jun 25 07:58:02 PM PDT 24 Jun 25 08:04:28 PM PDT 24 2343349101 ps
T1038 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3628794776 Jun 25 07:45:11 PM PDT 24 Jun 25 08:42:41 PM PDT 24 15377491128 ps
T1039 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2777432893 Jun 25 07:56:22 PM PDT 24 Jun 25 08:05:42 PM PDT 24 5850855444 ps
T377 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1636213833 Jun 25 07:56:10 PM PDT 24 Jun 25 07:58:40 PM PDT 24 2179486108 ps
T378 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2607691202 Jun 25 07:40:10 PM PDT 24 Jun 25 07:45:16 PM PDT 24 2847796256 ps
T1040 /workspace/coverage/default/52.chip_sw_all_escalation_resets.3290435535 Jun 25 08:14:48 PM PDT 24 Jun 25 08:25:52 PM PDT 24 5109591006 ps
T1041 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1449227931 Jun 25 08:08:44 PM PDT 24 Jun 25 08:12:38 PM PDT 24 3053394207 ps
T1042 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2488598144 Jun 25 07:57:39 PM PDT 24 Jun 25 08:20:54 PM PDT 24 8061591109 ps
T247 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4178971523 Jun 25 07:48:05 PM PDT 24 Jun 25 07:58:00 PM PDT 24 4266051304 ps
T295 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.641198339 Jun 25 08:00:38 PM PDT 24 Jun 25 09:26:10 PM PDT 24 48503391800 ps
T717 /workspace/coverage/default/0.chip_sw_all_escalation_resets.1499738036 Jun 25 07:38:36 PM PDT 24 Jun 25 07:46:48 PM PDT 24 5327251432 ps
T387 /workspace/coverage/default/2.chip_sw_kmac_app_rom.3088666316 Jun 25 08:05:06 PM PDT 24 Jun 25 08:10:02 PM PDT 24 2923480470 ps
T1043 /workspace/coverage/default/3.chip_sw_uart_tx_rx.3632506155 Jun 25 08:08:53 PM PDT 24 Jun 25 08:20:10 PM PDT 24 3636216216 ps
T1044 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3380038032 Jun 25 08:02:42 PM PDT 24 Jun 25 08:17:37 PM PDT 24 5737171732 ps
T1045 /workspace/coverage/default/2.rom_e2e_static_critical.3381155003 Jun 25 08:10:52 PM PDT 24 Jun 25 09:19:48 PM PDT 24 17099856912 ps
T741 /workspace/coverage/default/96.chip_sw_all_escalation_resets.4267070376 Jun 25 08:17:22 PM PDT 24 Jun 25 08:26:34 PM PDT 24 5786130272 ps
T1046 /workspace/coverage/default/1.chip_sw_hmac_multistream.10126065 Jun 25 07:54:21 PM PDT 24 Jun 25 08:23:19 PM PDT 24 7614677462 ps
T1047 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2015069316 Jun 25 07:51:15 PM PDT 24 Jun 25 08:00:22 PM PDT 24 3060389500 ps
T751 /workspace/coverage/default/53.chip_sw_all_escalation_resets.1714364766 Jun 25 08:15:36 PM PDT 24 Jun 25 08:24:45 PM PDT 24 5033395080 ps
T694 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4292823179 Jun 25 08:17:49 PM PDT 24 Jun 25 08:24:56 PM PDT 24 3692314810 ps
T684 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2294368398 Jun 25 08:13:12 PM PDT 24 Jun 25 08:20:39 PM PDT 24 4254240520 ps
T1048 /workspace/coverage/default/2.chip_tap_straps_dev.287300996 Jun 25 08:05:09 PM PDT 24 Jun 25 08:11:37 PM PDT 24 4540777500 ps
T1049 /workspace/coverage/default/0.chip_sw_power_idle_load.1102315997 Jun 25 07:43:23 PM PDT 24 Jun 25 07:54:32 PM PDT 24 4355212256 ps
T1050 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4150613687 Jun 25 08:05:14 PM PDT 24 Jun 25 08:14:15 PM PDT 24 3809736664 ps
T1051 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2919613633 Jun 25 07:39:13 PM PDT 24 Jun 25 07:54:37 PM PDT 24 5486075227 ps
T646 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2288205828 Jun 25 07:49:54 PM PDT 24 Jun 25 07:51:54 PM PDT 24 2483733179 ps
T1052 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3218885329 Jun 25 07:37:32 PM PDT 24 Jun 25 07:42:55 PM PDT 24 3092654284 ps
T1053 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2243633596 Jun 25 08:00:54 PM PDT 24 Jun 25 08:11:37 PM PDT 24 5546612241 ps
T725 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.884016106 Jun 25 08:14:14 PM PDT 24 Jun 25 08:20:42 PM PDT 24 3355634980 ps
T695 /workspace/coverage/default/45.chip_sw_all_escalation_resets.4086462594 Jun 25 08:13:54 PM PDT 24 Jun 25 08:26:00 PM PDT 24 4859052744 ps
T45 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.526229886 Jun 25 08:02:09 PM PDT 24 Jun 25 08:10:04 PM PDT 24 5240433840 ps
T374 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3027998287 Jun 25 07:48:10 PM PDT 24 Jun 25 09:35:48 PM PDT 24 24543964232 ps
T668 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.4107457090 Jun 25 07:39:02 PM PDT 24 Jun 25 07:44:27 PM PDT 24 3800235156 ps
T780 /workspace/coverage/default/5.chip_sw_all_escalation_resets.1958013873 Jun 25 08:10:52 PM PDT 24 Jun 25 08:23:48 PM PDT 24 5655168460 ps
T1054 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2202706498 Jun 25 07:39:03 PM PDT 24 Jun 25 07:51:33 PM PDT 24 6506748364 ps
T1055 /workspace/coverage/default/1.chip_sw_edn_sw_mode.4177099593 Jun 25 07:53:02 PM PDT 24 Jun 25 08:34:36 PM PDT 24 8595530940 ps
T1056 /workspace/coverage/default/2.chip_sw_csrng_kat_test.876767139 Jun 25 08:03:56 PM PDT 24 Jun 25 08:08:55 PM PDT 24 2451091280 ps
T1057 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2557675878 Jun 25 07:50:02 PM PDT 24 Jun 25 07:57:20 PM PDT 24 4748065036 ps
T201 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3686857879 Jun 25 07:40:10 PM PDT 24 Jun 25 07:47:08 PM PDT 24 3733080080 ps
T1058 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.723070530 Jun 25 08:05:31 PM PDT 24 Jun 25 08:14:12 PM PDT 24 3600172472 ps
T705 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2399727576 Jun 25 08:16:02 PM PDT 24 Jun 25 08:22:31 PM PDT 24 4022362408 ps
T389 /workspace/coverage/default/19.chip_sw_all_escalation_resets.829244841 Jun 25 08:11:56 PM PDT 24 Jun 25 08:26:25 PM PDT 24 6250172548 ps
T1059 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.624354628 Jun 25 07:51:25 PM PDT 24 Jun 25 07:53:13 PM PDT 24 2382070539 ps
T1060 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.991106434 Jun 25 08:01:26 PM PDT 24 Jun 25 08:24:39 PM PDT 24 13063193234 ps
T1061 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.36687902 Jun 25 07:58:09 PM PDT 24 Jun 25 08:03:54 PM PDT 24 2428185808 ps
T1062 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.1230800690 Jun 25 08:10:44 PM PDT 24 Jun 25 10:08:45 PM PDT 24 30723816956 ps
T1063 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1929452663 Jun 25 07:58:04 PM PDT 24 Jun 25 08:02:55 PM PDT 24 2984391656 ps
T1064 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3181853590 Jun 25 07:45:11 PM PDT 24 Jun 25 07:55:03 PM PDT 24 3789565920 ps
T1065 /workspace/coverage/default/0.chip_sw_power_sleep_load.1270245578 Jun 25 07:44:17 PM PDT 24 Jun 25 07:57:25 PM PDT 24 9891135680 ps
T1066 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1811159309 Jun 25 07:39:01 PM PDT 24 Jun 25 07:47:27 PM PDT 24 5400381096 ps
T1067 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.190028707 Jun 25 07:39:37 PM PDT 24 Jun 25 07:44:55 PM PDT 24 3931105859 ps
T1068 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2213906279 Jun 25 08:02:06 PM PDT 24 Jun 25 08:09:16 PM PDT 24 5422352374 ps
T1069 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2122394575 Jun 25 07:46:19 PM PDT 24 Jun 25 07:49:55 PM PDT 24 3162510470 ps
T749 /workspace/coverage/default/29.chip_sw_all_escalation_resets.3405349442 Jun 25 08:13:19 PM PDT 24 Jun 25 08:23:52 PM PDT 24 5446579956 ps
T1070 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2586149954 Jun 25 07:58:29 PM PDT 24 Jun 25 08:02:57 PM PDT 24 2399238164 ps
T1071 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4154551158 Jun 25 07:54:22 PM PDT 24 Jun 25 07:58:56 PM PDT 24 2729570100 ps
T1072 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.721251090 Jun 25 08:02:16 PM PDT 24 Jun 25 08:06:54 PM PDT 24 2520919250 ps
T1073 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2293074537 Jun 25 07:55:32 PM PDT 24 Jun 25 08:06:54 PM PDT 24 4356946120 ps
T1074 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1182785599 Jun 25 07:52:52 PM PDT 24 Jun 25 07:58:04 PM PDT 24 3403758444 ps
T1075 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2399338227 Jun 25 07:54:04 PM PDT 24 Jun 25 08:02:26 PM PDT 24 4914096218 ps
T1076 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1062852144 Jun 25 08:07:01 PM PDT 24 Jun 25 09:19:27 PM PDT 24 16623707560 ps
T1077 /workspace/coverage/default/0.chip_sival_flash_info_access.2430308597 Jun 25 07:39:00 PM PDT 24 Jun 25 07:44:02 PM PDT 24 2966901690 ps
T1078 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2132808072 Jun 25 07:43:40 PM PDT 24 Jun 25 07:56:42 PM PDT 24 6081153212 ps
T1079 /workspace/coverage/default/1.rom_keymgr_functest.3868739903 Jun 25 07:57:52 PM PDT 24 Jun 25 08:10:41 PM PDT 24 4870157200 ps
T1080 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2592288022 Jun 25 08:01:23 PM PDT 24 Jun 25 08:08:12 PM PDT 24 3799038322 ps
T1081 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3127363005 Jun 25 07:56:45 PM PDT 24 Jun 25 08:08:46 PM PDT 24 4614704992 ps
T47 /workspace/coverage/default/2.chip_sw_spi_device_tpm.2277280465 Jun 25 07:58:50 PM PDT 24 Jun 25 08:05:01 PM PDT 24 3516427653 ps
T1082 /workspace/coverage/default/1.chip_sw_kmac_idle.1834976006 Jun 25 07:55:11 PM PDT 24 Jun 25 07:58:42 PM PDT 24 2489989960 ps
T678 /workspace/coverage/default/1.chip_sw_pattgen_ios.1996782390 Jun 25 07:46:50 PM PDT 24 Jun 25 07:50:51 PM PDT 24 3177189500 ps
T776 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3695776389 Jun 25 08:18:14 PM PDT 24 Jun 25 08:25:21 PM PDT 24 4261307578 ps
T1083 /workspace/coverage/default/0.chip_sw_aes_smoketest.3220176520 Jun 25 07:45:31 PM PDT 24 Jun 25 07:50:01 PM PDT 24 3058053356 ps
T1084 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1474967510 Jun 25 07:44:36 PM PDT 24 Jun 25 08:40:07 PM PDT 24 31661558281 ps
T742 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2532340899 Jun 25 08:14:05 PM PDT 24 Jun 25 08:24:48 PM PDT 24 5877608120 ps
T290 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1091419430 Jun 25 08:04:35 PM PDT 24 Jun 25 09:13:16 PM PDT 24 15153904296 ps
T724 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2486142873 Jun 25 08:15:50 PM PDT 24 Jun 25 08:21:38 PM PDT 24 3087057040 ps
T1085 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4213197084 Jun 25 07:38:36 PM PDT 24 Jun 25 07:53:56 PM PDT 24 6439465408 ps
T1086 /workspace/coverage/default/1.rom_e2e_asm_init_dev.1361158936 Jun 25 08:01:48 PM PDT 24 Jun 25 09:03:11 PM PDT 24 16091659210 ps
T747 /workspace/coverage/default/97.chip_sw_all_escalation_resets.2161405528 Jun 25 08:18:21 PM PDT 24 Jun 25 08:30:58 PM PDT 24 5756546856 ps
T353 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3553535402 Jun 25 08:15:58 PM PDT 24 Jun 25 08:27:49 PM PDT 24 5274360664 ps
T1087 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.114929508 Jun 25 08:04:35 PM PDT 24 Jun 25 08:29:00 PM PDT 24 8387747596 ps
T1088 /workspace/coverage/default/1.chip_sw_edn_kat.83513449 Jun 25 07:53:07 PM PDT 24 Jun 25 08:02:32 PM PDT 24 3177826632 ps
T177 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.316230616 Jun 25 08:04:37 PM PDT 24 Jun 25 08:17:23 PM PDT 24 9744074341 ps
T721 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2831663282 Jun 25 08:13:30 PM PDT 24 Jun 25 08:24:06 PM PDT 24 4926052312 ps
T1089 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2985255925 Jun 25 07:37:46 PM PDT 24 Jun 25 08:19:51 PM PDT 24 9758439834 ps
T1090 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3341947162 Jun 25 07:50:06 PM PDT 24 Jun 25 08:09:42 PM PDT 24 13197817224 ps
T768 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1490069293 Jun 25 08:09:34 PM PDT 24 Jun 25 08:16:28 PM PDT 24 3308083360 ps
T729 /workspace/coverage/default/43.chip_sw_all_escalation_resets.531546092 Jun 25 08:13:19 PM PDT 24 Jun 25 08:24:17 PM PDT 24 5414698448 ps
T124 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3170293056 Jun 25 08:04:49 PM PDT 24 Jun 25 08:18:34 PM PDT 24 6439294728 ps
T101 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3838389284 Jun 25 07:39:05 PM PDT 24 Jun 25 07:46:53 PM PDT 24 6929294884 ps
T1091 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1940820242 Jun 25 07:42:57 PM PDT 24 Jun 25 07:48:56 PM PDT 24 4331969704 ps
T48 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2451513396 Jun 25 07:37:33 PM PDT 24 Jun 25 07:45:30 PM PDT 24 4079661761 ps
T1092 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2993992188 Jun 25 08:02:48 PM PDT 24 Jun 25 08:43:37 PM PDT 24 34776685114 ps
T125 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2546977764 Jun 25 07:42:54 PM PDT 24 Jun 25 07:49:44 PM PDT 24 5155583478 ps
T1093 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2758068629 Jun 25 07:42:20 PM PDT 24 Jun 25 08:04:42 PM PDT 24 5668977000 ps
T1094 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3080149830 Jun 25 07:59:29 PM PDT 24 Jun 25 08:13:39 PM PDT 24 6179448008 ps
T1095 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2117037945 Jun 25 08:10:30 PM PDT 24 Jun 25 08:26:11 PM PDT 24 8889283486 ps
T1096 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2953609592 Jun 25 07:57:42 PM PDT 24 Jun 25 08:25:14 PM PDT 24 10291982398 ps
T731 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1107265320 Jun 25 08:14:09 PM PDT 24 Jun 25 08:23:15 PM PDT 24 4205959256 ps
T71 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.4189396029 Jun 25 07:38:22 PM PDT 24 Jun 25 07:47:15 PM PDT 24 3640567056 ps
T1097 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.90472752 Jun 25 07:39:58 PM PDT 24 Jun 25 09:08:30 PM PDT 24 44747692754 ps
T1098 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3893232419 Jun 25 07:57:19 PM PDT 24 Jun 25 08:04:41 PM PDT 24 5749553560 ps
T1099 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2304677152 Jun 25 07:48:58 PM PDT 24 Jun 25 07:52:36 PM PDT 24 2976936898 ps
T1100 /workspace/coverage/default/1.chip_sw_example_rom.470835791 Jun 25 07:46:20 PM PDT 24 Jun 25 07:48:29 PM PDT 24 2224448808 ps
T331 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.721735833 Jun 25 08:05:28 PM PDT 24 Jun 25 08:13:03 PM PDT 24 3776703408 ps
T1101 /workspace/coverage/default/2.chip_sw_hmac_enc.1515652348 Jun 25 08:04:35 PM PDT 24 Jun 25 08:09:43 PM PDT 24 2219610136 ps
T1102 /workspace/coverage/default/0.chip_sw_aes_entropy.3453248988 Jun 25 07:42:04 PM PDT 24 Jun 25 07:45:50 PM PDT 24 3497346740 ps
T701 /workspace/coverage/default/81.chip_sw_all_escalation_resets.306819489 Jun 25 08:18:22 PM PDT 24 Jun 25 08:27:35 PM PDT 24 4927233862 ps
T1103 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2342321840 Jun 25 07:37:33 PM PDT 24 Jun 25 08:11:12 PM PDT 24 9199057055 ps
T1104 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.416012240 Jun 25 07:56:21 PM PDT 24 Jun 25 08:05:48 PM PDT 24 8436052002 ps
T750 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1970970938 Jun 25 08:17:33 PM PDT 24 Jun 25 08:28:37 PM PDT 24 5284761978 ps
T1105 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2561852742 Jun 25 08:09:26 PM PDT 24 Jun 25 08:13:50 PM PDT 24 2982522448 ps
T1106 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1078157771 Jun 25 08:05:40 PM PDT 24 Jun 25 08:10:15 PM PDT 24 2580363826 ps
T1107 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1723703830 Jun 25 08:08:23 PM PDT 24 Jun 25 08:23:45 PM PDT 24 5641972552 ps
T1108 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.4114281007 Jun 25 07:46:54 PM PDT 24 Jun 25 08:55:33 PM PDT 24 14379906250 ps
T727 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1258263035 Jun 25 08:12:53 PM PDT 24 Jun 25 08:19:15 PM PDT 24 3140788316 ps
T320 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.965798386 Jun 25 08:00:32 PM PDT 24 Jun 25 08:13:17 PM PDT 24 4478503980 ps
T375 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.339176469 Jun 25 07:47:43 PM PDT 24 Jun 25 09:33:57 PM PDT 24 24790686440 ps
T771 /workspace/coverage/default/94.chip_sw_all_escalation_resets.890796199 Jun 25 08:18:57 PM PDT 24 Jun 25 08:32:25 PM PDT 24 5582933250 ps
T1109 /workspace/coverage/default/86.chip_sw_all_escalation_resets.4000294693 Jun 25 08:16:43 PM PDT 24 Jun 25 08:26:26 PM PDT 24 6038503420 ps
T1110 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1854222007 Jun 25 08:08:29 PM PDT 24 Jun 25 08:24:10 PM PDT 24 8970660348 ps
T1111 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2916169297 Jun 25 08:08:37 PM PDT 24 Jun 25 08:20:34 PM PDT 24 5633931260 ps
T714 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1866139554 Jun 25 08:17:47 PM PDT 24 Jun 25 08:25:07 PM PDT 24 4059561256 ps
T1112 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2416093526 Jun 25 08:06:01 PM PDT 24 Jun 25 08:09:57 PM PDT 24 2766333029 ps
T388 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3657454562 Jun 25 07:54:16 PM PDT 24 Jun 25 08:00:06 PM PDT 24 3522923512 ps
T1113 /workspace/coverage/default/4.chip_tap_straps_prod.2096174140 Jun 25 08:09:32 PM PDT 24 Jun 25 08:34:38 PM PDT 24 14346829684 ps
T688 /workspace/coverage/default/42.chip_sw_all_escalation_resets.4007255245 Jun 25 08:13:11 PM PDT 24 Jun 25 08:25:04 PM PDT 24 6184003340 ps
T376 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1356076922 Jun 25 07:46:17 PM PDT 24 Jun 25 09:32:15 PM PDT 24 23758485688 ps
T325 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3486203375 Jun 25 07:59:42 PM PDT 24 Jun 25 08:16:43 PM PDT 24 5234005400 ps
T767 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2182956417 Jun 25 08:16:55 PM PDT 24 Jun 25 08:27:44 PM PDT 24 5009592920 ps
T1114 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.19086891 Jun 25 07:38:57 PM PDT 24 Jun 25 08:02:38 PM PDT 24 8503792498 ps
T357 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.4867252 Jun 25 07:59:10 PM PDT 24 Jun 25 08:08:38 PM PDT 24 4097250566 ps
T1115 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.55561883 Jun 25 08:00:47 PM PDT 24 Jun 25 08:06:28 PM PDT 24 2451539419 ps
T1116 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.3062758065 Jun 25 07:38:30 PM PDT 24 Jun 25 07:50:43 PM PDT 24 4260841666 ps
T1117 /workspace/coverage/default/0.chip_sw_example_rom.1455889847 Jun 25 07:36:23 PM PDT 24 Jun 25 07:38:48 PM PDT 24 3075718840 ps
T1118 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3827689836 Jun 25 07:57:40 PM PDT 24 Jun 25 08:02:42 PM PDT 24 2535811491 ps
T1119 /workspace/coverage/default/0.chip_sw_gpio_smoketest.3945597557 Jun 25 07:45:58 PM PDT 24 Jun 25 07:48:49 PM PDT 24 2425633547 ps
T12 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1919716293 Jun 25 07:37:34 PM PDT 24 Jun 25 07:42:41 PM PDT 24 4501797492 ps
T202 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3638705888 Jun 25 08:01:44 PM PDT 24 Jun 25 08:12:34 PM PDT 24 4684397965 ps
T1120 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3682021341 Jun 25 08:00:06 PM PDT 24 Jun 25 08:20:29 PM PDT 24 8053046552 ps
T730 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2398449676 Jun 25 08:17:34 PM PDT 24 Jun 25 08:29:03 PM PDT 24 5168120424 ps
T722 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1616309281 Jun 25 08:18:14 PM PDT 24 Jun 25 08:26:05 PM PDT 24 4083631658 ps
T248 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1142355627 Jun 25 07:39:50 PM PDT 24 Jun 25 07:42:04 PM PDT 24 3606947087 ps
T203 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3922137045 Jun 25 08:02:08 PM PDT 24 Jun 25 08:08:21 PM PDT 24 3205300593 ps
T1121 /workspace/coverage/default/0.rom_e2e_smoke.393671257 Jun 25 07:49:22 PM PDT 24 Jun 25 08:53:18 PM PDT 24 14525004764 ps
T1122 /workspace/coverage/default/0.chip_sw_hmac_smoketest.3694876838 Jun 25 07:45:36 PM PDT 24 Jun 25 07:52:22 PM PDT 24 3647222976 ps
T1123 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3309757972 Jun 25 08:05:03 PM PDT 24 Jun 25 08:15:58 PM PDT 24 4067335016 ps
T1124 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3569793517 Jun 25 07:40:19 PM PDT 24 Jun 25 08:02:07 PM PDT 24 7841871280 ps
T310 /workspace/coverage/default/1.chip_plic_all_irqs_20.366680397 Jun 25 07:54:59 PM PDT 24 Jun 25 08:06:29 PM PDT 24 4538770478 ps
T1125 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2718251997 Jun 25 08:17:12 PM PDT 24 Jun 25 08:26:45 PM PDT 24 5813040840 ps
T211 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1135332696 Jun 25 07:37:23 PM PDT 24 Jun 25 08:39:31 PM PDT 24 20906245216 ps
T1126 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.243651141 Jun 25 07:41:24 PM PDT 24 Jun 25 07:48:46 PM PDT 24 3430501408 ps
T1127 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2924135561 Jun 25 08:00:27 PM PDT 24 Jun 25 08:19:51 PM PDT 24 5190732039 ps
T287 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1265586015 Jun 25 07:54:09 PM PDT 24 Jun 25 08:39:22 PM PDT 24 11430295848 ps
T1128 /workspace/coverage/default/2.chip_sw_uart_tx_rx.2107210524 Jun 25 08:00:00 PM PDT 24 Jun 25 08:11:06 PM PDT 24 4737653200 ps
T759 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3632519352 Jun 25 08:18:27 PM PDT 24 Jun 25 08:27:39 PM PDT 24 4034265600 ps
T1129 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1105079317 Jun 25 07:49:14 PM PDT 24 Jun 25 07:53:42 PM PDT 24 3131256788 ps
T772 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1945706378 Jun 25 08:11:59 PM PDT 24 Jun 25 08:19:39 PM PDT 24 3866725880 ps
T1130 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1869789873 Jun 25 07:55:08 PM PDT 24 Jun 25 07:58:49 PM PDT 24 2774049000 ps
T745 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3619937647 Jun 25 08:14:05 PM PDT 24 Jun 25 08:22:22 PM PDT 24 3576483100 ps
T1131 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2304125442 Jun 25 08:16:34 PM PDT 24 Jun 25 08:21:45 PM PDT 24 3648792984 ps
T1132 /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2849413485 Jun 25 07:40:07 PM PDT 24 Jun 25 07:45:21 PM PDT 24 2742952280 ps
T770 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1713905984 Jun 25 08:16:56 PM PDT 24 Jun 25 08:23:46 PM PDT 24 3272737416 ps
T746 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3022390551 Jun 25 08:17:24 PM PDT 24 Jun 25 08:30:54 PM PDT 24 6321067864 ps
T1133 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1671693364 Jun 25 07:51:38 PM PDT 24 Jun 25 08:00:03 PM PDT 24 5004962264 ps
T160 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1922652344 Jun 25 08:06:29 PM PDT 24 Jun 25 08:19:05 PM PDT 24 5443959332 ps
T237 /workspace/coverage/default/65.chip_sw_all_escalation_resets.4073454835 Jun 25 08:15:29 PM PDT 24 Jun 25 08:25:42 PM PDT 24 4736231172 ps
T1134 /workspace/coverage/default/2.chip_sw_edn_sw_mode.2997349606 Jun 25 08:03:41 PM PDT 24 Jun 25 08:27:47 PM PDT 24 6840772136 ps
T1135 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.133476822 Jun 25 07:56:40 PM PDT 24 Jun 25 08:07:02 PM PDT 24 5708034570 ps
T1136 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1444599857 Jun 25 07:49:12 PM PDT 24 Jun 25 07:52:51 PM PDT 24 3120219400 ps
T1137 /workspace/coverage/default/2.chip_sw_hmac_oneshot.64499913 Jun 25 08:03:31 PM PDT 24 Jun 25 08:09:54 PM PDT 24 3551946688 ps
T1138 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3871534989 Jun 25 07:38:57 PM PDT 24 Jun 25 07:43:35 PM PDT 24 3324626888 ps
T297 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1132883053 Jun 25 07:39:35 PM PDT 24 Jun 25 09:20:34 PM PDT 24 50056135942 ps
T1139 /workspace/coverage/default/2.rom_volatile_raw_unlock.2674633123 Jun 25 08:08:43 PM PDT 24 Jun 25 08:10:49 PM PDT 24 2218199648 ps
T1140 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.155989169 Jun 25 08:09:17 PM PDT 24 Jun 25 08:39:21 PM PDT 24 8196953986 ps
T736 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3677973168 Jun 25 08:16:01 PM PDT 24 Jun 25 08:22:51 PM PDT 24 3772397352 ps
T270 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3058632031 Jun 25 07:57:11 PM PDT 24 Jun 25 08:01:58 PM PDT 24 3232356728 ps
T1141 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.3357666575 Jun 25 07:36:24 PM PDT 24 Jun 25 11:32:50 PM PDT 24 78386394936 ps
T335 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1899101418 Jun 25 07:49:59 PM PDT 24 Jun 25 08:01:39 PM PDT 24 3789617970 ps
T1142 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.596554029 Jun 25 07:42:25 PM PDT 24 Jun 25 07:50:54 PM PDT 24 4039916304 ps
T1143 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2409808835 Jun 25 07:37:13 PM PDT 24 Jun 25 07:48:18 PM PDT 24 3674097338 ps
T1144 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.689770686 Jun 25 08:10:46 PM PDT 24 Jun 25 08:56:38 PM PDT 24 13238067202 ps
T758 /workspace/coverage/default/15.chip_sw_all_escalation_resets.1514630199 Jun 25 08:12:07 PM PDT 24 Jun 25 08:26:38 PM PDT 24 5253123280 ps
T1145 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.563503664 Jun 25 08:11:14 PM PDT 24 Jun 25 08:23:34 PM PDT 24 7786767476 ps
T1146 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3859605774 Jun 25 07:36:36 PM PDT 24 Jun 25 07:59:36 PM PDT 24 8618331676 ps
T1147 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4010169878 Jun 25 07:40:22 PM PDT 24 Jun 25 08:15:37 PM PDT 24 12323018090 ps
T1148 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2016443085 Jun 25 08:04:28 PM PDT 24 Jun 25 08:12:35 PM PDT 24 4345838160 ps
T1149 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2095638346 Jun 25 08:05:46 PM PDT 24 Jun 25 08:16:24 PM PDT 24 5267912000 ps
T1150 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3929237229 Jun 25 08:05:19 PM PDT 24 Jun 25 08:19:51 PM PDT 24 4393562392 ps
T1151 /workspace/coverage/default/0.rom_e2e_static_critical.3107810360 Jun 25 07:48:01 PM PDT 24 Jun 25 09:03:07 PM PDT 24 17189561712 ps
T1152 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2670220556 Jun 25 07:40:38 PM PDT 24 Jun 25 07:45:15 PM PDT 24 2608075190 ps
T1153 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1828301510 Jun 25 08:10:57 PM PDT 24 Jun 25 08:19:54 PM PDT 24 4175221272 ps
T1154 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.2841205939 Jun 25 08:10:45 PM PDT 24 Jun 25 08:41:12 PM PDT 24 8508612750 ps
T733 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1000533002 Jun 25 07:47:14 PM PDT 24 Jun 25 08:00:31 PM PDT 24 5493841800 ps
T299 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1244375035 Jun 25 08:06:10 PM PDT 24 Jun 25 08:14:32 PM PDT 24 4202246288 ps
T1155 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.58155412 Jun 25 08:12:05 PM PDT 24 Jun 25 08:20:30 PM PDT 24 4730737324 ps
T128 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3799786194 Jun 25 08:10:29 PM PDT 24 Jun 25 08:22:47 PM PDT 24 4579542882 ps
T1156 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2165051728 Jun 25 08:10:29 PM PDT 24 Jun 25 08:36:05 PM PDT 24 7827695108 ps
T1157 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.602379366 Jun 25 07:45:13 PM PDT 24 Jun 25 07:51:52 PM PDT 24 3236755706 ps
T1158 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4284107757 Jun 25 07:39:28 PM PDT 24 Jun 25 07:49:14 PM PDT 24 4948058560 ps
T1159 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.4185410867 Jun 25 08:12:38 PM PDT 24 Jun 25 08:20:07 PM PDT 24 4043050220 ps
T1160 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3717747943 Jun 25 07:53:46 PM PDT 24 Jun 25 08:14:06 PM PDT 24 7836052364 ps
T1161 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1820890954 Jun 25 07:48:48 PM PDT 24 Jun 25 09:54:02 PM PDT 24 24944763324 ps
T1162 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1292227407 Jun 25 08:09:06 PM PDT 24 Jun 25 08:19:02 PM PDT 24 4443354598 ps
T503 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3873166687 Jun 25 07:40:12 PM PDT 24 Jun 25 07:55:32 PM PDT 24 4580974570 ps
T1163 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1673809391 Jun 25 07:54:52 PM PDT 24 Jun 25 08:01:40 PM PDT 24 3739690342 ps
T773 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.933976518 Jun 25 08:13:28 PM PDT 24 Jun 25 08:19:42 PM PDT 24 3548116900 ps
T740 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.930992936 Jun 25 08:13:40 PM PDT 24 Jun 25 08:20:13 PM PDT 24 3696524414 ps
T1164 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2637745484 Jun 25 07:51:59 PM PDT 24 Jun 25 07:57:00 PM PDT 24 3742553557 ps
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