| T1165 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3036067096 |
|
|
Jun 25 08:05:24 PM PDT 24 |
Jun 25 08:10:09 PM PDT 24 |
2749610053 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2197511065 |
|
|
Jun 25 08:08:05 PM PDT 24 |
Jun 25 08:26:26 PM PDT 24 |
5613227162 ps |
| T723 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2224501882 |
|
|
Jun 25 08:14:03 PM PDT 24 |
Jun 25 08:25:27 PM PDT 24 |
4890642152 ps |
| T1167 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3537051867 |
|
|
Jun 25 07:57:10 PM PDT 24 |
Jun 25 08:03:12 PM PDT 24 |
3394741854 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3504719698 |
|
|
Jun 25 07:57:03 PM PDT 24 |
Jun 25 08:03:38 PM PDT 24 |
6369102312 ps |
| T1169 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.696868521 |
|
|
Jun 25 08:03:04 PM PDT 24 |
Jun 25 08:35:24 PM PDT 24 |
9184523624 ps |
| T1170 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4247992832 |
|
|
Jun 25 08:10:13 PM PDT 24 |
Jun 25 08:20:18 PM PDT 24 |
6798502724 ps |
| T1171 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.4250451993 |
|
|
Jun 25 07:45:28 PM PDT 24 |
Jun 25 08:03:12 PM PDT 24 |
5396928780 ps |
| T1172 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1489518804 |
|
|
Jun 25 07:51:08 PM PDT 24 |
Jun 25 07:57:28 PM PDT 24 |
4403402776 ps |
| T142 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2873715851 |
|
|
Jun 25 07:59:21 PM PDT 24 |
Jun 25 11:18:50 PM PDT 24 |
58054995892 ps |
| T1173 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.991218338 |
|
|
Jun 25 08:02:16 PM PDT 24 |
Jun 25 08:56:27 PM PDT 24 |
11737163773 ps |
| T1174 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.83503668 |
|
|
Jun 25 07:59:48 PM PDT 24 |
Jun 25 08:08:40 PM PDT 24 |
5251815850 ps |
| T1175 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1648489592 |
|
|
Jun 25 07:54:17 PM PDT 24 |
Jun 25 08:34:18 PM PDT 24 |
11401067380 ps |
| T1176 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3225048205 |
|
|
Jun 25 07:40:32 PM PDT 24 |
Jun 25 07:48:04 PM PDT 24 |
4051817432 ps |
| T55 |
/workspace/coverage/default/0.chip_sw_alert_test.4170191443 |
|
|
Jun 25 07:40:37 PM PDT 24 |
Jun 25 07:45:58 PM PDT 24 |
2732003144 ps |
| T1177 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2108912882 |
|
|
Jun 25 07:47:01 PM PDT 24 |
Jun 25 11:26:04 PM PDT 24 |
77527697394 ps |
| T1178 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1161106701 |
|
|
Jun 25 07:56:20 PM PDT 24 |
Jun 25 08:04:17 PM PDT 24 |
4113489454 ps |
| T1179 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1357287372 |
|
|
Jun 25 08:11:30 PM PDT 24 |
Jun 25 08:19:43 PM PDT 24 |
5506185507 ps |
| T1180 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1398444712 |
|
|
Jun 25 08:11:21 PM PDT 24 |
Jun 25 08:19:23 PM PDT 24 |
4014498970 ps |
| T315 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2124037049 |
|
|
Jun 25 08:03:49 PM PDT 24 |
Jun 25 08:26:10 PM PDT 24 |
6166671160 ps |
| T687 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3199712446 |
|
|
Jun 25 08:16:36 PM PDT 24 |
Jun 25 08:26:44 PM PDT 24 |
4904847500 ps |
| T1181 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3120955242 |
|
|
Jun 25 07:39:08 PM PDT 24 |
Jun 25 07:51:10 PM PDT 24 |
4206985760 ps |
| T146 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.966910068 |
|
|
Jun 25 08:04:42 PM PDT 24 |
Jun 25 08:13:54 PM PDT 24 |
3170960584 ps |
| T392 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3836732120 |
|
|
Jun 25 08:05:37 PM PDT 24 |
Jun 25 08:30:33 PM PDT 24 |
21090158168 ps |
| T1182 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2195736768 |
|
|
Jun 25 07:39:57 PM PDT 24 |
Jun 25 08:50:11 PM PDT 24 |
17569257500 ps |
| T1183 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.939603713 |
|
|
Jun 25 07:57:52 PM PDT 24 |
Jun 25 08:06:22 PM PDT 24 |
5236523896 ps |
| T1184 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3403368434 |
|
|
Jun 25 07:51:13 PM PDT 24 |
Jun 25 08:00:17 PM PDT 24 |
7987531464 ps |
| T373 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3259970797 |
|
|
Jun 25 08:16:35 PM PDT 24 |
Jun 25 08:22:38 PM PDT 24 |
3605383640 ps |
| T179 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.598090635 |
|
|
Jun 25 07:39:39 PM PDT 24 |
Jun 25 07:48:02 PM PDT 24 |
4594635480 ps |
| T1185 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3981939678 |
|
|
Jun 25 07:49:58 PM PDT 24 |
Jun 25 08:55:23 PM PDT 24 |
15003110440 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_aes_enc.1994301187 |
|
|
Jun 25 08:03:19 PM PDT 24 |
Jun 25 08:07:26 PM PDT 24 |
2317060906 ps |
| T1187 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3304992340 |
|
|
Jun 25 07:40:26 PM PDT 24 |
Jun 25 07:45:10 PM PDT 24 |
3117942504 ps |
| T1188 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1741241988 |
|
|
Jun 25 08:11:16 PM PDT 24 |
Jun 25 08:19:54 PM PDT 24 |
3904411692 ps |
| T1189 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.733533464 |
|
|
Jun 25 08:02:37 PM PDT 24 |
Jun 25 08:11:21 PM PDT 24 |
7622760346 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.3356239974 |
|
|
Jun 25 08:08:05 PM PDT 24 |
Jun 25 08:12:20 PM PDT 24 |
3267867876 ps |
| T1191 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.3613422332 |
|
|
Jun 25 07:39:32 PM PDT 24 |
Jun 25 07:55:58 PM PDT 24 |
5805471608 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2691674348 |
|
|
Jun 25 07:50:00 PM PDT 24 |
Jun 25 07:54:10 PM PDT 24 |
3563246880 ps |
| T1193 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2610857293 |
|
|
Jun 25 08:14:20 PM PDT 24 |
Jun 25 08:21:46 PM PDT 24 |
3932375468 ps |
| T1194 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4274570686 |
|
|
Jun 25 07:40:02 PM PDT 24 |
Jun 25 07:51:45 PM PDT 24 |
5238291032 ps |
| T161 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.537956137 |
|
|
Jun 25 07:38:58 PM PDT 24 |
Jun 25 07:47:20 PM PDT 24 |
4309439048 ps |
| T763 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.4293457944 |
|
|
Jun 25 08:16:52 PM PDT 24 |
Jun 25 08:26:59 PM PDT 24 |
4539177620 ps |
| T1195 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3611907241 |
|
|
Jun 25 08:05:54 PM PDT 24 |
Jun 25 08:22:38 PM PDT 24 |
8064146290 ps |
| T1196 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2439788660 |
|
|
Jun 25 08:17:18 PM PDT 24 |
Jun 25 08:27:09 PM PDT 24 |
4344380620 ps |
| T1197 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1827826931 |
|
|
Jun 25 07:38:44 PM PDT 24 |
Jun 25 07:49:31 PM PDT 24 |
4524760000 ps |
| T312 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3581278941 |
|
|
Jun 25 07:37:35 PM PDT 24 |
Jun 25 08:13:47 PM PDT 24 |
11569553140 ps |
| T180 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.804872768 |
|
|
Jun 25 08:02:34 PM PDT 24 |
Jun 25 08:14:19 PM PDT 24 |
4301336316 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.99942956 |
|
|
Jun 25 07:49:20 PM PDT 24 |
Jun 25 09:32:50 PM PDT 24 |
50820506350 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.657684353 |
|
|
Jun 25 07:40:33 PM PDT 24 |
Jun 25 09:13:22 PM PDT 24 |
20524742488 ps |
| T1200 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2402708941 |
|
|
Jun 25 08:18:15 PM PDT 24 |
Jun 25 08:28:37 PM PDT 24 |
4745137558 ps |
| T1201 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1342426619 |
|
|
Jun 25 07:54:45 PM PDT 24 |
Jun 25 08:03:35 PM PDT 24 |
5314589974 ps |
| T1202 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3622312854 |
|
|
Jun 25 07:50:33 PM PDT 24 |
Jun 25 07:57:01 PM PDT 24 |
3059251368 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1908697677 |
|
|
Jun 25 08:00:40 PM PDT 24 |
Jun 25 08:09:07 PM PDT 24 |
6866771864 ps |
| T396 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1942414575 |
|
|
Jun 25 08:17:29 PM PDT 24 |
Jun 25 08:25:28 PM PDT 24 |
5587103912 ps |
| T1204 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1662265410 |
|
|
Jun 25 07:42:25 PM PDT 24 |
Jun 25 07:52:23 PM PDT 24 |
5163117728 ps |
| T1205 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.30726011 |
|
|
Jun 25 08:13:20 PM PDT 24 |
Jun 25 08:26:08 PM PDT 24 |
4770160688 ps |
| T1206 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1940589760 |
|
|
Jun 25 08:07:46 PM PDT 24 |
Jun 25 08:14:56 PM PDT 24 |
2961520180 ps |
| T1207 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1351966004 |
|
|
Jun 25 08:02:28 PM PDT 24 |
Jun 25 08:08:12 PM PDT 24 |
2797395440 ps |
| T1208 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3074132258 |
|
|
Jun 25 07:59:23 PM PDT 24 |
Jun 25 08:09:39 PM PDT 24 |
3690153212 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3377796786 |
|
|
Jun 25 07:39:25 PM PDT 24 |
Jun 25 07:53:26 PM PDT 24 |
4301652880 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3609225756 |
|
|
Jun 25 07:56:20 PM PDT 24 |
Jun 25 08:10:46 PM PDT 24 |
6392558527 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4113521629 |
|
|
Jun 25 07:54:47 PM PDT 24 |
Jun 25 08:06:05 PM PDT 24 |
4302558142 ps |
| T1212 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3436589609 |
|
|
Jun 25 08:02:44 PM PDT 24 |
Jun 25 08:56:17 PM PDT 24 |
20288741791 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2210404311 |
|
|
Jun 25 07:59:19 PM PDT 24 |
Jun 25 08:16:48 PM PDT 24 |
5353021880 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.4243110513 |
|
|
Jun 25 07:48:51 PM PDT 24 |
Jun 25 07:57:12 PM PDT 24 |
3926465520 ps |
| T34 |
/workspace/coverage/default/0.chip_sw_gpio.1282868321 |
|
|
Jun 25 07:38:40 PM PDT 24 |
Jun 25 07:47:38 PM PDT 24 |
3426930952 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3222352834 |
|
|
Jun 25 08:00:19 PM PDT 24 |
Jun 25 08:11:30 PM PDT 24 |
5057172229 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3009235299 |
|
|
Jun 25 07:39:54 PM PDT 24 |
Jun 25 07:50:38 PM PDT 24 |
5288633298 ps |
| T1215 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3433579717 |
|
|
Jun 25 08:01:51 PM PDT 24 |
Jun 25 08:05:46 PM PDT 24 |
2126334884 ps |
| T1216 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2341986518 |
|
|
Jun 25 07:58:48 PM PDT 24 |
Jun 25 08:11:49 PM PDT 24 |
4829728280 ps |
| T1217 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1857117164 |
|
|
Jun 25 07:55:47 PM PDT 24 |
Jun 25 08:04:36 PM PDT 24 |
3434964368 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3150060927 |
|
|
Jun 25 07:52:48 PM PDT 24 |
Jun 25 08:12:55 PM PDT 24 |
6747876592 ps |
| T1219 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3187858079 |
|
|
Jun 25 07:37:25 PM PDT 24 |
Jun 25 09:16:51 PM PDT 24 |
49372781888 ps |
| T1220 |
/workspace/coverage/default/2.chip_sw_aes_idle.3113466099 |
|
|
Jun 25 08:02:49 PM PDT 24 |
Jun 25 08:08:41 PM PDT 24 |
3430508120 ps |
| T1221 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3632680835 |
|
|
Jun 25 07:59:14 PM PDT 24 |
Jun 25 11:14:07 PM PDT 24 |
64208422125 ps |
| T1222 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3910735351 |
|
|
Jun 25 07:41:25 PM PDT 24 |
Jun 25 09:32:28 PM PDT 24 |
48467514842 ps |
| T1223 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.438153496 |
|
|
Jun 25 07:39:21 PM PDT 24 |
Jun 25 07:47:27 PM PDT 24 |
5423030710 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_aes_enc.3340531482 |
|
|
Jun 25 07:51:23 PM PDT 24 |
Jun 25 07:55:47 PM PDT 24 |
3001896138 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.3680361751 |
|
|
Jun 25 07:58:39 PM PDT 24 |
Jun 25 08:04:01 PM PDT 24 |
2953181080 ps |
| T1226 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.957260429 |
|
|
Jun 25 08:02:11 PM PDT 24 |
Jun 25 08:07:39 PM PDT 24 |
3453894008 ps |
| T1227 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2969070498 |
|
|
Jun 25 08:09:44 PM PDT 24 |
Jun 25 08:19:40 PM PDT 24 |
3808308952 ps |
| T711 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.901849318 |
|
|
Jun 25 08:14:49 PM PDT 24 |
Jun 25 08:24:23 PM PDT 24 |
5596085936 ps |
| T249 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.921537416 |
|
|
Jun 25 07:38:01 PM PDT 24 |
Jun 25 07:46:06 PM PDT 24 |
9587138991 ps |
| T1228 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1535721560 |
|
|
Jun 25 08:00:45 PM PDT 24 |
Jun 25 08:21:48 PM PDT 24 |
8959576400 ps |
| T1229 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.654230809 |
|
|
Jun 25 08:11:11 PM PDT 24 |
Jun 25 08:16:48 PM PDT 24 |
3417200024 ps |
| T1230 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.241340148 |
|
|
Jun 25 08:14:40 PM PDT 24 |
Jun 25 08:25:52 PM PDT 24 |
6211449176 ps |
| T1231 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1120612771 |
|
|
Jun 25 08:06:25 PM PDT 24 |
Jun 25 08:10:17 PM PDT 24 |
2538048002 ps |
| T1232 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.3625540417 |
|
|
Jun 25 08:12:21 PM PDT 24 |
Jun 25 09:12:27 PM PDT 24 |
16205760500 ps |
| T738 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1291625684 |
|
|
Jun 25 08:16:45 PM PDT 24 |
Jun 25 08:26:59 PM PDT 24 |
5670992420 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.182059187 |
|
|
Jun 25 07:40:50 PM PDT 24 |
Jun 25 07:45:02 PM PDT 24 |
2849994552 ps |
| T689 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2774669066 |
|
|
Jun 25 08:15:55 PM PDT 24 |
Jun 25 08:21:45 PM PDT 24 |
3363427664 ps |
| T1234 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.962295092 |
|
|
Jun 25 07:40:41 PM PDT 24 |
Jun 25 07:45:34 PM PDT 24 |
2485433465 ps |
| T229 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2820498980 |
|
|
Jun 25 07:39:46 PM PDT 24 |
Jun 25 07:43:58 PM PDT 24 |
3012350424 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3778972368 |
|
|
Jun 25 07:39:34 PM PDT 24 |
Jun 25 08:50:11 PM PDT 24 |
18538774794 ps |
| T316 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1632011575 |
|
|
Jun 25 07:56:30 PM PDT 24 |
Jun 25 08:18:17 PM PDT 24 |
6408462976 ps |
| T56 |
/workspace/coverage/default/1.chip_sw_alert_test.1010551223 |
|
|
Jun 25 07:52:56 PM PDT 24 |
Jun 25 07:59:53 PM PDT 24 |
3088029720 ps |
| T1236 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.530925419 |
|
|
Jun 25 08:11:44 PM PDT 24 |
Jun 25 08:42:17 PM PDT 24 |
7635601414 ps |
| T129 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1265836994 |
|
|
Jun 25 08:08:14 PM PDT 24 |
Jun 25 08:22:16 PM PDT 24 |
6324059228 ps |
| T1237 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2167587214 |
|
|
Jun 25 08:09:40 PM PDT 24 |
Jun 25 08:30:13 PM PDT 24 |
11305401994 ps |
| T1238 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1201696001 |
|
|
Jun 25 07:39:03 PM PDT 24 |
Jun 25 08:30:27 PM PDT 24 |
28057462691 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3407356851 |
|
|
Jun 25 07:58:23 PM PDT 24 |
Jun 25 08:03:50 PM PDT 24 |
2909535390 ps |
| T1240 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3111314240 |
|
|
Jun 25 08:12:43 PM PDT 24 |
Jun 25 09:08:14 PM PDT 24 |
15521210142 ps |
| T774 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3927846441 |
|
|
Jun 25 08:15:15 PM PDT 24 |
Jun 25 08:20:33 PM PDT 24 |
3404426408 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1133929634 |
|
|
Jun 25 07:38:31 PM PDT 24 |
Jun 25 07:50:13 PM PDT 24 |
5575588920 ps |
| T1242 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.618988442 |
|
|
Jun 25 07:51:47 PM PDT 24 |
Jun 25 07:59:59 PM PDT 24 |
17547999004 ps |
| T1243 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.681217965 |
|
|
Jun 25 07:51:45 PM PDT 24 |
Jun 25 08:54:44 PM PDT 24 |
18668438618 ps |
| T1244 |
/workspace/coverage/default/1.chip_tap_straps_dev.3059247248 |
|
|
Jun 25 07:55:50 PM PDT 24 |
Jun 25 07:59:25 PM PDT 24 |
2978020738 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3679712493 |
|
|
Jun 25 08:00:21 PM PDT 24 |
Jun 25 08:02:19 PM PDT 24 |
2600417595 ps |
| T67 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.667471437 |
|
|
Jun 25 08:08:36 PM PDT 24 |
Jun 25 08:15:29 PM PDT 24 |
4225178144 ps |
| T20 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2845512347 |
|
|
Jun 25 07:58:36 PM PDT 24 |
Jun 25 08:03:09 PM PDT 24 |
3124491550 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3382916355 |
|
|
Jun 25 07:50:43 PM PDT 24 |
Jun 25 07:55:11 PM PDT 24 |
2651188067 ps |
| T1247 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.329285516 |
|
|
Jun 25 08:02:48 PM PDT 24 |
Jun 25 11:48:13 PM PDT 24 |
255379127282 ps |
| T1248 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4009520783 |
|
|
Jun 25 07:38:07 PM PDT 24 |
Jun 25 07:50:08 PM PDT 24 |
4540429320 ps |
| T1249 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1885442105 |
|
|
Jun 25 07:39:37 PM PDT 24 |
Jun 25 07:45:17 PM PDT 24 |
3726093168 ps |
| T1250 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1175463845 |
|
|
Jun 25 07:58:56 PM PDT 24 |
Jun 26 12:04:47 AM PDT 24 |
78908953800 ps |
| T1251 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1576196122 |
|
|
Jun 25 08:09:13 PM PDT 24 |
Jun 25 08:14:46 PM PDT 24 |
5890528982 ps |
| T691 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2281063447 |
|
|
Jun 25 08:17:11 PM PDT 24 |
Jun 25 08:24:59 PM PDT 24 |
3426899944 ps |
| T1252 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2804105401 |
|
|
Jun 25 08:16:44 PM PDT 24 |
Jun 25 08:26:40 PM PDT 24 |
4885843096 ps |
| T313 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3843707888 |
|
|
Jun 25 07:49:40 PM PDT 24 |
Jun 25 08:25:11 PM PDT 24 |
12668597136 ps |
| T1253 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1473594505 |
|
|
Jun 25 07:57:14 PM PDT 24 |
Jun 25 08:19:13 PM PDT 24 |
5880264574 ps |
| T1254 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1553431960 |
|
|
Jun 25 07:40:08 PM PDT 24 |
Jun 25 07:51:25 PM PDT 24 |
4241262390 ps |
| T131 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3989491745 |
|
|
Jun 25 07:58:47 PM PDT 24 |
Jun 25 08:07:40 PM PDT 24 |
5334467768 ps |
| T1255 |
/workspace/coverage/default/1.chip_tap_straps_rma.1790499388 |
|
|
Jun 25 07:56:02 PM PDT 24 |
Jun 25 08:04:28 PM PDT 24 |
5464461034 ps |
| T735 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2062432252 |
|
|
Jun 25 08:10:16 PM PDT 24 |
Jun 25 08:16:05 PM PDT 24 |
3286236144 ps |
| T1256 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1871831346 |
|
|
Jun 25 08:08:22 PM PDT 24 |
Jun 25 08:19:08 PM PDT 24 |
4196008956 ps |
| T1257 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3956764405 |
|
|
Jun 25 08:01:29 PM PDT 24 |
Jun 25 08:16:22 PM PDT 24 |
10241575764 ps |
| T347 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.2640344281 |
|
|
Jun 25 07:59:42 PM PDT 24 |
Jun 25 08:03:59 PM PDT 24 |
2576641140 ps |
| T1258 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2302129114 |
|
|
Jun 25 07:49:32 PM PDT 24 |
Jun 25 08:51:16 PM PDT 24 |
11515641078 ps |
| T1259 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3432845501 |
|
|
Jun 25 08:01:49 PM PDT 24 |
Jun 25 08:34:55 PM PDT 24 |
21589818377 ps |
| T1260 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2584466428 |
|
|
Jun 25 07:54:54 PM PDT 24 |
Jun 25 08:09:38 PM PDT 24 |
4404722660 ps |
| T1261 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3471101986 |
|
|
Jun 25 08:10:13 PM PDT 24 |
Jun 25 09:26:16 PM PDT 24 |
18853234760 ps |
| T757 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.4156121739 |
|
|
Jun 25 08:17:50 PM PDT 24 |
Jun 25 08:26:07 PM PDT 24 |
3812607712 ps |
| T57 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.207827360 |
|
|
Jun 25 07:41:05 PM PDT 24 |
Jun 25 07:51:54 PM PDT 24 |
5167440960 ps |
| T1262 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3659831154 |
|
|
Jun 25 07:46:36 PM PDT 24 |
Jun 25 09:13:53 PM PDT 24 |
17830388486 ps |
| T1263 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1083220284 |
|
|
Jun 25 08:10:33 PM PDT 24 |
Jun 25 08:22:13 PM PDT 24 |
3768371110 ps |
| T1264 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2324357311 |
|
|
Jun 25 07:59:49 PM PDT 24 |
Jun 25 08:14:20 PM PDT 24 |
4400437640 ps |
| T1265 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3792461296 |
|
|
Jun 25 08:07:29 PM PDT 24 |
Jun 25 08:14:22 PM PDT 24 |
7109702804 ps |
| T1266 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.364730102 |
|
|
Jun 25 07:41:10 PM PDT 24 |
Jun 25 07:47:30 PM PDT 24 |
3243815540 ps |
| T1267 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3977249576 |
|
|
Jun 25 07:46:05 PM PDT 24 |
Jun 25 07:50:24 PM PDT 24 |
2985084720 ps |
| T322 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3757536657 |
|
|
Jun 25 08:06:32 PM PDT 24 |
Jun 25 08:26:06 PM PDT 24 |
6149375896 ps |
| T712 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.329121410 |
|
|
Jun 25 08:13:44 PM PDT 24 |
Jun 25 08:20:03 PM PDT 24 |
3457952768 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.759799501 |
|
|
Jun 25 07:37:58 PM PDT 24 |
Jun 25 07:41:43 PM PDT 24 |
2753068384 ps |
| T676 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1444234849 |
|
|
Jun 25 08:05:00 PM PDT 24 |
Jun 25 08:32:16 PM PDT 24 |
20895919518 ps |
| T1268 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1325214374 |
|
|
Jun 25 08:04:49 PM PDT 24 |
Jun 25 08:18:36 PM PDT 24 |
4648396490 ps |
| T778 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.498340656 |
|
|
Jun 25 08:14:46 PM PDT 24 |
Jun 25 08:22:51 PM PDT 24 |
4386330424 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1513546540 |
|
|
Jun 25 07:38:25 PM PDT 24 |
Jun 25 08:01:38 PM PDT 24 |
9870443764 ps |
| T1270 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3434336345 |
|
|
Jun 25 07:41:03 PM PDT 24 |
Jun 25 08:09:09 PM PDT 24 |
14498483710 ps |
| T1271 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3317254954 |
|
|
Jun 25 07:41:13 PM PDT 24 |
Jun 25 07:47:12 PM PDT 24 |
4875424672 ps |
| T1272 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1931259156 |
|
|
Jun 25 07:57:08 PM PDT 24 |
Jun 25 08:00:43 PM PDT 24 |
2556964744 ps |
| T1273 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2639954502 |
|
|
Jun 25 08:05:00 PM PDT 24 |
Jun 25 08:16:12 PM PDT 24 |
4295751836 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1987981462 |
|
|
Jun 25 07:54:57 PM PDT 24 |
Jun 25 08:46:43 PM PDT 24 |
20117298648 ps |
| T1275 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1884545525 |
|
|
Jun 25 07:52:17 PM PDT 24 |
Jun 25 08:16:09 PM PDT 24 |
16757078891 ps |
| T327 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1769731144 |
|
|
Jun 25 07:47:51 PM PDT 24 |
Jun 25 08:00:28 PM PDT 24 |
5047499416 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.441917135 |
|
|
Jun 25 07:38:15 PM PDT 24 |
Jun 25 07:41:59 PM PDT 24 |
2806460834 ps |
| T775 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3411227772 |
|
|
Jun 25 08:18:23 PM PDT 24 |
Jun 25 08:24:07 PM PDT 24 |
3637502592 ps |
| T1277 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1218250276 |
|
|
Jun 25 07:53:44 PM PDT 24 |
Jun 25 07:58:15 PM PDT 24 |
2533206880 ps |
| T1278 |
/workspace/coverage/default/2.chip_sw_example_rom.3212408893 |
|
|
Jun 25 07:57:13 PM PDT 24 |
Jun 25 07:59:51 PM PDT 24 |
1970572100 ps |
| T130 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.562157389 |
|
|
Jun 25 07:39:49 PM PDT 24 |
Jun 25 07:54:35 PM PDT 24 |
6181567748 ps |
| T1279 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2862897908 |
|
|
Jun 25 07:40:55 PM PDT 24 |
Jun 25 07:59:41 PM PDT 24 |
6408909402 ps |
| T1280 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.449444105 |
|
|
Jun 25 07:46:54 PM PDT 24 |
Jun 25 08:39:42 PM PDT 24 |
13269980914 ps |
| T1281 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1920087857 |
|
|
Jun 25 08:11:34 PM PDT 24 |
Jun 25 08:25:21 PM PDT 24 |
5912339500 ps |
| T369 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3298225853 |
|
|
Jun 25 07:40:39 PM PDT 24 |
Jun 25 07:57:25 PM PDT 24 |
5873578136 ps |
| T1282 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.3199179974 |
|
|
Jun 25 07:41:05 PM PDT 24 |
Jun 25 07:50:08 PM PDT 24 |
5653887381 ps |
| T1283 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2878860006 |
|
|
Jun 25 08:00:47 PM PDT 24 |
Jun 25 09:17:56 PM PDT 24 |
15461394236 ps |
| T360 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3293265481 |
|
|
Jun 25 07:40:32 PM PDT 24 |
Jun 25 08:08:24 PM PDT 24 |
6701030128 ps |
| T328 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.8732690 |
|
|
Jun 25 07:36:47 PM PDT 24 |
Jun 25 07:46:33 PM PDT 24 |
4743760412 ps |
| T1284 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1590909728 |
|
|
Jun 25 08:11:10 PM PDT 24 |
Jun 25 08:24:54 PM PDT 24 |
9427023481 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.1285998275 |
|
|
Jun 25 07:37:35 PM PDT 24 |
Jun 25 07:47:50 PM PDT 24 |
3738998660 ps |
| T1286 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2629260342 |
|
|
Jun 25 07:58:05 PM PDT 24 |
Jun 25 08:04:42 PM PDT 24 |
3116396470 ps |
| T1287 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.2225757102 |
|
|
Jun 25 08:07:29 PM PDT 24 |
Jun 25 08:12:23 PM PDT 24 |
3308302700 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2909523045 |
|
|
Jun 25 07:58:03 PM PDT 24 |
Jun 25 08:04:22 PM PDT 24 |
3478924580 ps |
| T1289 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2734450300 |
|
|
Jun 25 08:04:42 PM PDT 24 |
Jun 25 08:29:11 PM PDT 24 |
8371312110 ps |
| T1290 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2726428272 |
|
|
Jun 25 08:08:33 PM PDT 24 |
Jun 25 08:18:10 PM PDT 24 |
4597782154 ps |
| T1291 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.2782035628 |
|
|
Jun 25 07:57:29 PM PDT 24 |
Jun 25 08:03:28 PM PDT 24 |
2839961548 ps |
| T1292 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3377092385 |
|
|
Jun 25 08:12:43 PM PDT 24 |
Jun 25 08:18:59 PM PDT 24 |
4087184728 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.2537118259 |
|
|
Jun 25 08:04:53 PM PDT 24 |
Jun 25 08:29:25 PM PDT 24 |
7524568904 ps |
| T1294 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3635444980 |
|
|
Jun 25 08:01:14 PM PDT 24 |
Jun 25 08:13:30 PM PDT 24 |
4948949220 ps |
| T1295 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.4095242565 |
|
|
Jun 25 08:02:05 PM PDT 24 |
Jun 25 08:08:44 PM PDT 24 |
3057552590 ps |
| T1296 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1240352636 |
|
|
Jun 25 07:52:21 PM PDT 24 |
Jun 25 08:22:28 PM PDT 24 |
9671565400 ps |
| T194 |
/workspace/coverage/default/1.chip_jtag_mem_access.1997787215 |
|
|
Jun 25 07:48:33 PM PDT 24 |
Jun 25 08:14:05 PM PDT 24 |
13758449400 ps |
| T1297 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1541712756 |
|
|
Jun 25 07:55:59 PM PDT 24 |
Jun 25 08:26:16 PM PDT 24 |
13106420194 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3374733064 |
|
|
Jun 25 08:01:23 PM PDT 24 |
Jun 25 08:07:51 PM PDT 24 |
5529770408 ps |
| T777 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2234683896 |
|
|
Jun 25 08:12:40 PM PDT 24 |
Jun 25 08:18:25 PM PDT 24 |
3404930178 ps |
| T1299 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.515897428 |
|
|
Jun 25 07:49:19 PM PDT 24 |
Jun 25 08:01:17 PM PDT 24 |
4294812142 ps |
| T1300 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.768361000 |
|
|
Jun 25 08:00:23 PM PDT 24 |
Jun 25 08:03:01 PM PDT 24 |
2914177955 ps |
| T1301 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.904447567 |
|
|
Jun 25 07:40:06 PM PDT 24 |
Jun 25 07:43:24 PM PDT 24 |
3017261624 ps |
| T1302 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.4271791135 |
|
|
Jun 25 07:48:00 PM PDT 24 |
Jun 25 08:21:07 PM PDT 24 |
8353917627 ps |
| T195 |
/workspace/coverage/default/0.chip_jtag_mem_access.2431035795 |
|
|
Jun 25 07:31:26 PM PDT 24 |
Jun 25 07:52:58 PM PDT 24 |
14123720052 ps |
| T1303 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3532936453 |
|
|
Jun 25 08:11:21 PM PDT 24 |
Jun 25 08:22:51 PM PDT 24 |
3929862352 ps |
| T1304 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2537130797 |
|
|
Jun 25 08:00:36 PM PDT 24 |
Jun 25 08:13:13 PM PDT 24 |
4605682728 ps |
| T1305 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.1425260235 |
|
|
Jun 25 07:37:00 PM PDT 24 |
Jun 25 07:40:56 PM PDT 24 |
2771082016 ps |
| T655 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1065952985 |
|
|
Jun 25 08:17:27 PM PDT 24 |
Jun 25 08:30:34 PM PDT 24 |
5317746692 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.449157135 |
|
|
Jun 25 07:54:53 PM PDT 24 |
Jun 25 08:07:52 PM PDT 24 |
4254779910 ps |
| T1307 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3458113984 |
|
|
Jun 25 07:49:03 PM PDT 24 |
Jun 25 08:57:52 PM PDT 24 |
15225495460 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.4096649238 |
|
|
Jun 25 07:52:15 PM PDT 24 |
Jun 25 07:56:38 PM PDT 24 |
2593318366 ps |
| T639 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2951949881 |
|
|
Jun 25 07:39:56 PM PDT 24 |
Jun 25 07:48:36 PM PDT 24 |
2919488528 ps |
| T748 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.3199956018 |
|
|
Jun 25 08:11:21 PM PDT 24 |
Jun 25 08:22:05 PM PDT 24 |
5464606040 ps |
| T1309 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1639228143 |
|
|
Jun 25 08:05:01 PM PDT 24 |
Jun 25 08:12:58 PM PDT 24 |
8404828334 ps |
| T1310 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.2649211266 |
|
|
Jun 25 07:50:56 PM PDT 24 |
Jun 25 07:57:15 PM PDT 24 |
3805998710 ps |
| T713 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.107143019 |
|
|
Jun 25 08:15:55 PM PDT 24 |
Jun 25 08:26:11 PM PDT 24 |
4973971720 ps |
| T1311 |
/workspace/coverage/default/0.rom_keymgr_functest.274539007 |
|
|
Jun 25 07:45:23 PM PDT 24 |
Jun 25 07:53:17 PM PDT 24 |
5199430442 ps |
| T238 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1273592494 |
|
|
Jun 25 08:01:46 PM PDT 24 |
Jun 25 08:09:14 PM PDT 24 |
5284083980 ps |
| T271 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3065289075 |
|
|
Jun 25 07:41:58 PM PDT 24 |
Jun 25 07:45:41 PM PDT 24 |
2153300936 ps |
| T1312 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1318821469 |
|
|
Jun 25 07:39:25 PM PDT 24 |
Jun 25 07:46:40 PM PDT 24 |
3968538826 ps |
| T1313 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.938332414 |
|
|
Jun 25 07:38:24 PM PDT 24 |
Jun 25 07:56:27 PM PDT 24 |
5559290040 ps |
| T178 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1133012569 |
|
|
Jun 25 07:38:08 PM PDT 24 |
Jun 25 07:52:25 PM PDT 24 |
7842049685 ps |
| T764 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1321958930 |
|
|
Jun 25 08:16:29 PM PDT 24 |
Jun 25 08:23:10 PM PDT 24 |
4344853448 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1421829992 |
|
|
Jun 25 07:53:55 PM PDT 24 |
Jun 25 08:00:41 PM PDT 24 |
3355839976 ps |
| T272 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2588456058 |
|
|
Jun 25 08:05:54 PM PDT 24 |
Jun 25 08:10:46 PM PDT 24 |
3385258354 ps |
| T761 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3140657127 |
|
|
Jun 25 08:13:15 PM PDT 24 |
Jun 25 08:23:32 PM PDT 24 |
4487368934 ps |
| T1314 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3500238157 |
|
|
Jun 25 07:42:00 PM PDT 24 |
Jun 25 08:16:40 PM PDT 24 |
6611500510 ps |
| T1315 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.3987314673 |
|
|
Jun 25 07:39:20 PM PDT 24 |
Jun 25 07:50:17 PM PDT 24 |
4907006078 ps |
| T779 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.4272982020 |
|
|
Jun 25 08:12:07 PM PDT 24 |
Jun 25 08:21:32 PM PDT 24 |
4087137048 ps |
| T14 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1296137690 |
|
|
Jun 25 07:56:09 PM PDT 24 |
Jun 25 08:04:01 PM PDT 24 |
4876454104 ps |
| T311 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.613797090 |
|
|
Jun 25 07:42:52 PM PDT 24 |
Jun 25 07:56:21 PM PDT 24 |
4144013312 ps |
| T1316 |
/workspace/coverage/default/2.chip_sw_edn_kat.1768848068 |
|
|
Jun 25 08:02:40 PM PDT 24 |
Jun 25 08:14:41 PM PDT 24 |
3308700410 ps |
| T1317 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3885258939 |
|
|
Jun 25 08:08:02 PM PDT 24 |
Jun 25 08:18:22 PM PDT 24 |
3709373132 ps |
| T1318 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3234696070 |
|
|
Jun 25 07:46:44 PM PDT 24 |
Jun 25 07:50:49 PM PDT 24 |
2808126012 ps |
| T79 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1778982449 |
|
|
Jun 25 07:48:36 PM PDT 24 |
Jun 25 08:04:23 PM PDT 24 |
9189399889 ps |
| T1319 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.839868646 |
|
|
Jun 25 07:57:58 PM PDT 24 |
Jun 25 08:06:53 PM PDT 24 |
9119546448 ps |
| T1320 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.296496026 |
|
|
Jun 25 08:00:22 PM PDT 24 |
Jun 25 09:29:25 PM PDT 24 |
48717455822 ps |
| T73 |
/workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1158854356 |
|
|
Jun 25 08:29:45 PM PDT 24 |
Jun 25 08:31:52 PM PDT 24 |
10828584290 ps |
| T74 |
/workspace/coverage/cover_reg_top/14.chip_csr_rw.830532418 |
|
|
Jun 25 08:19:27 PM PDT 24 |
Jun 25 08:28:39 PM PDT 24 |
4574285000 ps |
| T75 |
/workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3937253013 |
|
|
Jun 25 08:26:36 PM PDT 24 |
Jun 25 08:26:45 PM PDT 24 |
50883073 ps |
| T78 |
/workspace/coverage/cover_reg_top/92.xbar_random_large_delays.3302184366 |
|
|
Jun 25 08:33:37 PM PDT 24 |
Jun 25 08:51:20 PM PDT 24 |
98923790092 ps |
| T118 |
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.986336723 |
|
|
Jun 25 08:11:51 PM PDT 24 |
Jun 25 08:21:58 PM PDT 24 |
30234222490 ps |
| T278 |
/workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.893058830 |
|
|
Jun 25 08:32:45 PM PDT 24 |
Jun 25 08:32:52 PM PDT 24 |
36959927 ps |
| T225 |
/workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3646992913 |
|
|
Jun 25 08:28:20 PM PDT 24 |
Jun 25 08:28:40 PM PDT 24 |
117559810 ps |
| T393 |
/workspace/coverage/cover_reg_top/22.xbar_random_large_delays.367239742 |
|
|
Jun 25 08:21:34 PM PDT 24 |
Jun 25 08:39:45 PM PDT 24 |
92244387539 ps |
| T432 |
/workspace/coverage/cover_reg_top/72.xbar_same_source.3200007788 |
|
|
Jun 25 08:30:39 PM PDT 24 |
Jun 25 08:31:15 PM PDT 24 |
460155219 ps |
| T226 |
/workspace/coverage/cover_reg_top/95.xbar_same_source.2034963070 |
|
|
Jun 25 08:34:02 PM PDT 24 |
Jun 25 08:35:02 PM PDT 24 |
1938102825 ps |
| T227 |
/workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.1865769040 |
|
|
Jun 25 08:14:34 PM PDT 24 |
Jun 25 08:16:49 PM PDT 24 |
7183246348 ps |
| T138 |
/workspace/coverage/cover_reg_top/7.chip_csr_rw.3939333762 |
|
|
Jun 25 08:16:23 PM PDT 24 |
Jun 25 08:26:35 PM PDT 24 |
5823436100 ps |
| T139 |
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2869042429 |
|
|
Jun 25 08:18:00 PM PDT 24 |
Jun 25 08:49:38 PM PDT 24 |
16530239099 ps |
| T508 |
/workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.3235262687 |
|
|
Jun 25 08:31:47 PM PDT 24 |
Jun 25 08:43:33 PM PDT 24 |
39449715209 ps |
| T710 |
/workspace/coverage/cover_reg_top/85.xbar_access_same_device.3361492693 |
|
|
Jun 25 08:32:21 PM PDT 24 |
Jun 25 08:33:22 PM PDT 24 |
1201346047 ps |
| T511 |
/workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3010895747 |
|
|
Jun 25 08:30:02 PM PDT 24 |
Jun 25 08:30:12 PM PDT 24 |
39715477 ps |
| T515 |
/workspace/coverage/cover_reg_top/66.xbar_random_large_delays.2817492348 |
|
|
Jun 25 08:29:32 PM PDT 24 |
Jun 25 08:30:41 PM PDT 24 |
5648367452 ps |
| T509 |
/workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2419628471 |
|
|
Jun 25 08:24:33 PM PDT 24 |
Jun 25 08:25:28 PM PDT 24 |
3144447841 ps |
| T513 |
/workspace/coverage/cover_reg_top/86.xbar_random.3059379512 |
|
|
Jun 25 08:32:37 PM PDT 24 |
Jun 25 08:32:50 PM PDT 24 |
104617136 ps |
| T512 |
/workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1402357599 |
|
|
Jun 25 08:34:08 PM PDT 24 |
Jun 25 08:35:48 PM PDT 24 |
8571721477 ps |
| T423 |
/workspace/coverage/cover_reg_top/19.xbar_stress_all.3723933466 |
|
|
Jun 25 08:21:01 PM PDT 24 |
Jun 25 08:27:27 PM PDT 24 |
4180135425 ps |
| T514 |
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2639941459 |
|
|
Jun 25 08:18:07 PM PDT 24 |
Jun 25 08:19:52 PM PDT 24 |
8669556034 ps |
| T416 |
/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3921409899 |
|
|
Jun 25 08:29:30 PM PDT 24 |
Jun 25 08:31:13 PM PDT 24 |
270688097 ps |
| T417 |
/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.27899314 |
|
|
Jun 25 08:32:33 PM PDT 24 |
Jun 25 08:36:39 PM PDT 24 |
3458129383 ps |
| T510 |
/workspace/coverage/cover_reg_top/78.xbar_error_random.24999006 |
|
|
Jun 25 08:31:24 PM PDT 24 |
Jun 25 08:32:48 PM PDT 24 |
2028659517 ps |
| T507 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.2926899591 |
|
|
Jun 25 08:19:27 PM PDT 24 |
Jun 25 08:24:37 PM PDT 24 |
1620709070 ps |
| T1321 |
/workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1671319741 |
|
|
Jun 25 08:27:19 PM PDT 24 |
Jun 25 08:27:30 PM PDT 24 |
45338108 ps |
| T452 |
/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.3909974969 |
|
|
Jun 25 08:17:10 PM PDT 24 |
Jun 25 08:28:55 PM PDT 24 |
11919503496 ps |
| T681 |
/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1648194177 |
|
|
Jun 25 08:24:32 PM PDT 24 |
Jun 25 08:27:00 PM PDT 24 |
641912348 ps |
| T367 |
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1121028339 |
|
|
Jun 25 08:19:46 PM PDT 24 |
Jun 25 08:48:06 PM PDT 24 |
15296291729 ps |