Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3613122	1			T74	1602		T75	18		T76	488
values[2]	714256	1			T74	505		T75	18		T76	43
values[3]	99940	1			T74	17		T75	19		T78	4
values[4]	53995	1			T75	18		T502	18		T80	104
values[5]	36184	1			T75	18		T502	18		T80	74
values[6]	26701	1			T75	18		T502	18		T80	56
values[7]	22188	1			T75	18		T502	18		T80	92
values[8]	18942	1			T75	18		T502	19		T80	82
values[9]	17299	1			T75	18		T502	18		T80	81
values[10]	15784	1			T75	18		T502	18		T80	71
values[11]	14232	1			T75	18		T502	18		T80	58
values[12]	13083	1			T75	18		T502	18		T80	76
values[13]	12713	1			T75	19		T502	18		T80	77
values[14]	12164	1			T75	18		T502	18		T80	78
values[15]	11769	1			T75	18		T502	19		T80	69
values[16]	11505	1			T75	19		T502	19		T80	78
values[17]	10933	1			T75	19		T502	18		T80	74
values[18]	10526	1			T75	19		T502	18		T80	85
values[19]	10164	1			T75	18		T502	18		T80	78
values[20]	9940	1			T75	18		T502	18		T80	81
values[21]	9519	1			T75	18		T502	18		T80	52
values[22]	9138	1			T75	19		T502	18		T80	64
values[23]	9079	1			T75	18		T502	19		T80	73
values[24]	8760	1			T75	18		T502	18		T80	57
values[25]	8536	1			T75	18		T502	19		T80	51
values[26]	8101	1			T75	18		T502	18		T80	57
values[27]	7886	1			T75	18		T502	18		T80	59
values[28]	7578	1			T75	18		T502	18		T80	45
values[29]	7156	1			T75	18		T502	18		T80	34
values[30]	6608	1			T75	19		T502	19		T80	38
values[31]	6196	1			T75	18		T502	18		T80	26
values[32]	5777	1			T75	19		T502	18		T80	25
values[33]	5258	1			T75	18		T502	18		T80	25
values[34]	4972	1			T75	19		T502	18		T80	14
values[35]	4710	1			T75	18		T502	18		T80	31
values[36]	4475	1			T75	18		T502	18		T80	6
values[37]	4205	1			T75	18		T502	19		T80	3
values[38]	3985	1			T75	18		T502	20		T80	6
values[39]	3926	1			T75	19		T502	18		T80	5
values[40]	3793	1			T75	18		T502	18		T80	5
values[41]	3634	1			T75	18		T502	18		T80	7
values[42]	3637	1			T75	19		T502	19		T80	4
values[43]	3404	1			T75	18		T502	18		T80	1
values[44]	3424	1			T75	18		T502	18		T80	3
values[45]	3308	1			T75	18		T502	18		T80	2
values[46]	3180	1			T75	19		T502	19		T80	2
values[47]	3244	1			T75	18		T502	19		T80	1
values[48]	3200	1			T75	18		T502	18		T80	1
values[49]	3113	1			T75	18		T502	18		T80	3
values[50]	3009	1			T75	18		T502	18		T80	3
values[51]	2940	1			T75	18		T502	18		T80	5
values[52]	2962	1			T75	18		T502	18		T80	2
values[53]	2878	1			T75	18		T502	19		T80	3
values[54]	2826	1			T75	18		T502	18		T80	5
values[55]	2840	1			T75	19		T502	18		T80	2
values[56]	2695	1			T75	19		T502	18		T715	8
values[57]	2638	1			T75	18		T502	18		T715	8
values[58]	2599	1			T75	18		T502	18		T715	8
values[59]	2564	1			T75	18		T502	19		T715	8
values[60]	2637	1			T75	20		T502	18		T715	8
values[61]	2755	1			T75	18		T502	18		T715	8
values[62]	4066	1			T75	18		T502	18		T715	8
values[63]	10831	1			T75	23		T502	19		T715	8
values[64]	260641	1			T75	3400		T502	3223		T715	1584

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4649589	1			T74	1779		T75	2879		T76	584
values[2]	790627	1			T74	439		T75	827		T76	32
values[3]	83246	1			T74	47		T75	240		T78	5
values[4]	14875	1			T74	1		T75	79		T78	1
values[5]	5502	1			T75	30		T502	25		T715	15
values[6]	3211	1			T75	10		T502	8		T715	3
values[7]	2438	1			T75	3		T502	2		T715	2
values[8]	2099	1			T75	1		T502	1		T715	2
values[9]	1812	1			T75	1		T502	1		T715	2
values[10]	1462	1			T75	1		T502	1		T715	1
values[11]	1399	1			T75	1		T502	1		T715	1
values[12]	1207	1			T75	1		T502	1		T715	1
values[13]	1107	1			T75	1		T502	1		T715	1
values[14]	989	1			T75	1		T502	1		T715	1
values[15]	1063	1			T75	1		T502	1		T715	1
values[16]	986	1			T75	1		T502	1		T715	1
values[17]	946	1			T75	1		T502	1		T715	1
values[18]	878	1			T75	2		T502	1		T715	1
values[19]	930	1			T75	1		T502	1		T715	1
values[20]	841	1			T75	1		T502	1		T715	1
values[21]	818	1			T75	1		T502	1		T715	1
values[22]	806	1			T75	1		T502	1		T715	1
values[23]	769	1			T75	1		T502	1		T715	1
values[24]	698	1			T75	1		T502	1		T715	1
values[25]	683	1			T75	1		T502	1		T715	1
values[26]	723	1			T75	1		T502	1		T715	1
values[27]	634	1			T75	1		T502	1		T715	1
values[28]	619	1			T75	1		T502	1		T715	1
values[29]	652	1			T75	1		T502	1		T715	1
values[30]	655	1			T75	1		T502	1		T715	1
values[31]	559	1			T75	1		T502	1		T715	1
values[32]	544	1			T75	1		T502	1		T715	1
values[33]	551	1			T75	1		T502	1		T715	1
values[34]	545	1			T75	1		T502	1		T715	1
values[35]	523	1			T75	1		T502	1		T715	1
values[36]	506	1			T75	1		T502	1		T715	1
values[37]	511	1			T75	1		T502	1		T715	1
values[38]	527	1			T75	1		T502	1		T715	1
values[39]	499	1			T75	1		T502	1		T715	1
values[40]	475	1			T75	1		T502	1		T715	1
values[41]	491	1			T75	1		T502	2		T715	1
values[42]	504	1			T75	1		T502	1		T715	1
values[43]	487	1			T75	1		T502	1		T715	1
values[44]	466	1			T75	1		T502	1		T715	1
values[45]	462	1			T75	1		T502	1		T715	1
values[46]	488	1			T75	1		T502	1		T715	1
values[47]	476	1			T75	1		T502	1		T715	1
values[48]	448	1			T75	1		T502	1		T715	1
values[49]	449	1			T75	1		T502	1		T715	1
values[50]	424	1			T75	1		T502	1		T715	1
values[51]	446	1			T75	1		T502	1		T715	1
values[52]	435	1			T75	1		T502	1		T715	1
values[53]	398	1			T75	1		T502	1		T715	1
values[54]	421	1			T75	1		T502	1		T715	1
values[55]	447	1			T75	1		T502	1		T715	1
values[56]	425	1			T75	1		T502	1		T715	1
values[57]	390	1			T75	1		T502	1		T715	1
values[58]	357	1			T75	1		T502	1		T715	1
values[59]	369	1			T75	1		T502	1		T715	1
values[60]	354	1			T75	1		T502	1		T715	1
values[61]	413	1			T75	1		T502	1		T715	1
values[62]	692	1			T75	1		T502	1		T715	1
values[63]	2239	1			T75	2		T502	1		T715	2
values[64]	28180	1			T75	227		T502	160		T715	144

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	563439	1			T74	23		T75	18		T76	5
values[2]	2616350	1			T74	1172		T75	18		T76	551
values[3]	1072846	1			T74	721		T75	18		T76	44
values[4]	141640	1			T74	23		T75	18		T78	2
values[5]	73884	1			T75	18		T502	18		T80	122
values[6]	48297	1			T75	18		T502	18		T80	86
values[7]	34533	1			T75	18		T502	18		T80	86
values[8]	26824	1			T75	18		T502	18		T80	93
values[9]	23129	1			T75	18		T502	18		T80	95
values[10]	20134	1			T75	18		T502	18		T80	95
values[11]	18126	1			T75	18		T502	18		T80	63
values[12]	16851	1			T75	18		T502	18		T80	61
values[13]	16154	1			T75	18		T502	18		T80	88
values[14]	15146	1			T75	18		T502	18		T80	69
values[15]	14372	1			T75	18		T502	18		T80	46
values[16]	14107	1			T75	18		T502	18		T80	46
values[17]	13733	1			T75	18		T502	18		T80	40
values[18]	12836	1			T75	18		T502	18		T80	56
values[19]	12141	1			T75	18		T502	18		T80	67
values[20]	11664	1			T75	18		T502	18		T80	106
values[21]	11382	1			T75	18		T502	18		T80	89
values[22]	10719	1			T75	18		T502	18		T80	71
values[23]	10346	1			T75	18		T502	18		T80	94
values[24]	10078	1			T75	18		T502	18		T80	86
values[25]	9297	1			T75	18		T502	19		T80	70
values[26]	8887	1			T75	18		T502	18		T80	60
values[27]	8755	1			T75	18		T502	18		T80	70
values[28]	8516	1			T75	18		T502	18		T80	52
values[29]	8051	1			T75	19		T502	18		T80	22
values[30]	7425	1			T75	18		T502	18		T80	19
values[31]	6831	1			T75	18		T502	18		T80	29
values[32]	6319	1			T75	18		T502	18		T80	16
values[33]	5559	1			T75	18		T502	18		T80	23
values[34]	5421	1			T75	18		T502	18		T80	11
values[35]	5140	1			T75	18		T502	19		T80	12
values[36]	4779	1			T75	18		T502	18		T80	8
values[37]	4445	1			T75	18		T502	18		T80	14
values[38]	4324	1			T75	18		T502	18		T80	8
values[39]	4112	1			T75	18		T502	18		T80	10
values[40]	4071	1			T75	18		T502	18		T80	15
values[41]	3890	1			T75	18		T502	18		T80	11
values[42]	3846	1			T75	18		T502	19		T80	16
values[43]	3705	1			T75	18		T502	18		T80	2
values[44]	3652	1			T75	18		T502	18		T80	3
values[45]	3598	1			T75	18		T502	18		T80	2
values[46]	3662	1			T75	19		T502	18		T80	3
values[47]	3529	1			T75	18		T502	18		T80	2
values[48]	3433	1			T75	18		T502	19		T80	7
values[49]	3406	1			T75	18		T502	18		T80	1
values[50]	3366	1			T75	18		T502	18		T80	2
values[51]	3210	1			T75	18		T502	18		T80	1
values[52]	3151	1			T75	18		T502	18		T80	1
values[53]	3181	1			T75	18		T502	19		T80	1
values[54]	2990	1			T75	18		T502	18		T80	1
values[55]	2976	1			T75	18		T502	18		T80	7
values[56]	2968	1			T75	18		T502	18		T80	1
values[57]	2949	1			T75	18		T502	18		T80	1
values[58]	2848	1			T75	19		T502	18		T80	2
values[59]	2760	1			T75	18		T502	19		T80	1
values[60]	2817	1			T75	18		T502	18		T80	9
values[61]	2883	1			T75	18		T502	19		T715	8
values[62]	3630	1			T75	18		T502	18		T715	8
values[63]	8683	1			T75	21		T502	18		T715	8
values[64]	254407	1			T75	3318		T502	3282		T715	1507