Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2117684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32497631

1

T4

5590

T5

63904

T6

6980

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23252406	1			T4	2328		T5	57235		T6	3037
values[0x0]	9594788	1			T4	3262		T5	6669		T6	3943
values[0x1]	1768121	1			T4	397		T5	380		T6	290

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	493780	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34121535

1

T4

5987

T5

64284

T6

7270

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16365316	1			T4	2994		T5	32143		T6	3635
valid_sources[0x01]	16364338	1			T4	2993		T5	32141		T6	3635
valid_sources[0x02]	30163	1			T77	2		T190	2		T503	20
valid_sources[0x03]	29052	1			T189	1		T190	1		T503	13
valid_sources[0x04]	32300	1			T77	1		T503	21		T131	801
valid_sources[0x05]	29884	1			T71	1		T190	3		T503	23
valid_sources[0x06]	29876	1			T190	2		T503	16		T131	788
valid_sources[0x07]	29924	1			T503	17		T131	751		T362	233
valid_sources[0x08]	31551	1			T71	1		T189	11		T503	26
valid_sources[0x09]	31739	1			T20	39		T71	3		T503	14
valid_sources[0x0a]	29456	1			T503	56		T131	815		T362	176
valid_sources[0x0b]	31518	1			T503	24		T131	790		T362	175
valid_sources[0x0c]	30117	1			T71	4		T188	1		T189	3
valid_sources[0x0d]	29373	1			T503	20		T131	753		T362	171
valid_sources[0x0e]	29989	1			T503	8		T131	825		T362	185
valid_sources[0x0f]	29718	1			T189	2		T503	14		T131	795
valid_sources[0x10]	30074	1			T71	3		T189	4		T190	3
valid_sources[0x11]	30226	1			T77	1		T503	28		T131	822
valid_sources[0x12]	30361	1			T503	5		T131	841		T362	129
valid_sources[0x13]	30353	1			T503	19		T131	826		T362	165
valid_sources[0x14]	29486	1			T71	1		T190	2		T503	15
valid_sources[0x15]	30153	1			T188	4		T190	1		T503	13
valid_sources[0x16]	29221	1			T190	1		T503	14		T131	810
valid_sources[0x17]	30989	1			T189	11		T190	3		T503	23
valid_sources[0x18]	30506	1			T188	3		T503	14		T131	846
valid_sources[0x19]	30425	1			T71	1		T188	8		T503	20
valid_sources[0x1a]	29805	1			T188	8		T503	15		T131	808
valid_sources[0x1b]	29531	1			T71	4		T503	17		T131	829
valid_sources[0x1c]	29834	1			T190	2		T503	24		T131	773
valid_sources[0x1d]	30363	1			T71	1		T77	4		T190	1
valid_sources[0x1e]	30371	1			T188	1		T503	17		T131	792
valid_sources[0x1f]	30330	1			T190	3		T503	23		T131	762
valid_sources[0x20]	30214	1			T503	21		T131	819		T362	170

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22725671

1

T4

2328

T5

57235

T6

3037

values[0x0]

all_enables

biggest_size

9550263

1

T4

3262

T5

6669

T6

3943

values[0x1]

all_enables

biggest_size

221697

1

T20

23

T71

20

T77

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2852138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452293

1

T74

6

T75

593

T76

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1118281	1			T74	40		T75	1577		T76	6
values[0x0]	1067476	1			T74	8		T75	1469		T76	3
values[0x1]	1118674	1			T74	45		T75	1509		T76	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2208141	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1096290

1

T74

32

T75

1488

T76

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51398	1			T74	4		T75	76		T78	2
valid_sources[0x01]	51044	1			T74	2		T75	74		T76	1
valid_sources[0x02]	53421	1			T74	3		T75	70		T78	3
valid_sources[0x03]	51483	1			T74	1		T75	64		T502	66
valid_sources[0x04]	52478	1			T74	1		T75	84		T76	2
valid_sources[0x05]	51549	1			T75	82		T79	34		T502	81
valid_sources[0x06]	51217	1			T74	1		T75	64		T78	1
valid_sources[0x07]	51317	1			T74	2		T75	64		T78	1
valid_sources[0x08]	51545	1			T74	3		T75	71		T79	5
valid_sources[0x09]	52115	1			T74	1		T75	78		T79	1
valid_sources[0x0a]	51472	1			T74	4		T75	66		T78	3
valid_sources[0x0b]	50957	1			T74	2		T75	81		T76	1
valid_sources[0x0c]	51627	1			T74	1		T75	70		T76	1
valid_sources[0x0d]	51237	1			T75	57		T76	1		T79	2
valid_sources[0x0e]	52628	1			T74	2		T75	82		T76	1
valid_sources[0x0f]	52899	1			T74	1		T75	70		T78	1
valid_sources[0x10]	53223	1			T74	2		T75	60		T78	4
valid_sources[0x11]	51879	1			T75	79		T78	3		T502	62
valid_sources[0x12]	51618	1			T74	2		T75	65		T76	1
valid_sources[0x13]	51496	1			T75	66		T78	2		T502	71
valid_sources[0x14]	51921	1			T75	70		T78	3		T502	72
valid_sources[0x15]	52489	1			T74	2		T75	88		T78	1
valid_sources[0x16]	51093	1			T74	2		T75	73		T502	73
valid_sources[0x17]	51469	1			T75	61		T76	1		T78	6
valid_sources[0x18]	52820	1			T75	67		T76	1		T78	2
valid_sources[0x19]	50602	1			T74	3		T75	78		T78	1
valid_sources[0x1a]	51741	1			T75	83		T79	4		T502	66
valid_sources[0x1b]	51767	1			T74	1		T75	80		T76	1
valid_sources[0x1c]	51985	1			T74	2		T75	74		T78	1
valid_sources[0x1d]	50964	1			T74	5		T75	83		T78	2
valid_sources[0x1e]	51996	1			T74	2		T75	63		T76	2
valid_sources[0x1f]	50657	1			T74	1		T75	67		T78	2
valid_sources[0x20]	50517	1			T75	77		T79	14		T502	50

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47303

1

T74

2

T75

60

T76

2

values[0x0]

all_enables

biggest_size

357459

1

T74

1

T75

479

T76

3

values[0x1]

all_enables

biggest_size

47531

1

T74

3

T75

54

T78

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3040119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

495195

1

T74

10

T75

612

T76

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1209252	1			T74	39		T75	1489		T76	16
values[0x0]	1115467	1			T74	6		T75	1406		T76	2
values[0x1]	1210595	1			T74	38		T75	1458		T76	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2334452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1200862

1

T74

34

T75

1478

T76

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55289	1			T75	76		T78	3		T79	15
valid_sources[0x01]	55537	1			T74	1		T75	81		T78	1
valid_sources[0x02]	55250	1			T75	71		T78	1		T79	9
valid_sources[0x03]	55351	1			T74	1		T75	55		T76	2
valid_sources[0x04]	54996	1			T74	4		T75	94		T78	1
valid_sources[0x05]	55044	1			T74	1		T75	78		T78	7
valid_sources[0x06]	55084	1			T75	86		T76	1		T78	2
valid_sources[0x07]	55962	1			T74	3		T75	57		T78	4
valid_sources[0x08]	55737	1			T74	2		T75	80		T76	2
valid_sources[0x09]	55615	1			T74	1		T75	45		T78	3
valid_sources[0x0a]	55070	1			T74	1		T75	89		T79	6
valid_sources[0x0b]	54519	1			T75	36		T79	9		T502	48
valid_sources[0x0c]	55376	1			T74	1		T75	74		T78	1
valid_sources[0x0d]	54090	1			T74	4		T75	94		T78	3
valid_sources[0x0e]	56094	1			T74	2		T75	92		T76	1
valid_sources[0x0f]	56181	1			T74	3		T75	92		T78	2
valid_sources[0x10]	54873	1			T74	1		T75	58		T78	3
valid_sources[0x11]	55883	1			T74	1		T75	53		T76	2
valid_sources[0x12]	55989	1			T74	3		T75	43		T78	3
valid_sources[0x13]	54682	1			T75	71		T76	1		T78	2
valid_sources[0x14]	55847	1			T74	3		T75	49		T78	9
valid_sources[0x15]	56419	1			T74	1		T75	99		T78	1
valid_sources[0x16]	55071	1			T74	1		T75	86		T78	2
valid_sources[0x17]	54708	1			T75	67		T78	1		T79	14
valid_sources[0x18]	56184	1			T75	60		T79	12		T502	66
valid_sources[0x19]	54952	1			T74	1		T75	86		T78	2
valid_sources[0x1a]	56664	1			T74	2		T75	73		T78	1
valid_sources[0x1b]	55528	1			T75	61		T76	5		T78	1
valid_sources[0x1c]	53429	1			T74	1		T75	94		T78	1
valid_sources[0x1d]	54169	1			T74	1		T75	93		T79	6
valid_sources[0x1e]	55302	1			T74	1		T75	33		T78	3
valid_sources[0x1f]	54803	1			T74	1		T75	93		T76	2
valid_sources[0x20]	55874	1			T74	2		T75	60		T76	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51761

1

T74

5

T75

58

T76

1

values[0x0]

all_enables

biggest_size

391273

1

T74

3

T75

496

T76

1

values[0x1]

all_enables

biggest_size

52161

1

T74

2

T75

58

T76

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2874235	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

454780

1

T74

6

T75

626

T76

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1126235	1			T74	40		T75	1546		T76	17
values[0x0]	1076887	1			T74	8		T75	1466		T76	2
values[0x1]	1125893	1			T74	39		T75	1446		T76	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2225403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1103612

1

T74

30

T75

1465

T76

15

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52245	1			T75	76		T79	1		T502	63
valid_sources[0x01]	51844	1			T74	4		T75	68		T76	1
valid_sources[0x02]	52223	1			T74	2		T75	77		T76	1
valid_sources[0x03]	51730	1			T74	2		T75	70		T76	4
valid_sources[0x04]	52337	1			T74	1		T75	59		T76	1
valid_sources[0x05]	52329	1			T74	1		T75	80		T78	2
valid_sources[0x06]	51813	1			T74	2		T75	84		T78	7
valid_sources[0x07]	52249	1			T74	3		T75	79		T76	1
valid_sources[0x08]	52016	1			T74	1		T75	67		T76	1
valid_sources[0x09]	52007	1			T75	57		T79	9		T502	70
valid_sources[0x0a]	51447	1			T74	1		T75	80		T76	1
valid_sources[0x0b]	50921	1			T74	1		T75	55		T76	1
valid_sources[0x0c]	52529	1			T74	1		T75	65		T78	2
valid_sources[0x0d]	51220	1			T74	3		T75	64		T79	11
valid_sources[0x0e]	52097	1			T74	3		T75	63		T502	74
valid_sources[0x0f]	53325	1			T74	2		T75	65		T78	3
valid_sources[0x10]	51912	1			T74	2		T75	55		T79	3
valid_sources[0x11]	51747	1			T74	2		T75	67		T78	1
valid_sources[0x12]	52501	1			T74	1		T75	79		T79	1
valid_sources[0x13]	51281	1			T74	1		T75	79		T76	1
valid_sources[0x14]	53226	1			T75	74		T76	1		T79	2
valid_sources[0x15]	52234	1			T75	66		T79	10		T502	74
valid_sources[0x16]	51111	1			T74	5		T75	77		T79	10
valid_sources[0x17]	51981	1			T74	1		T75	63		T78	2
valid_sources[0x18]	52191	1			T75	68		T76	1		T79	33
valid_sources[0x19]	51473	1			T75	73		T78	4		T502	75
valid_sources[0x1a]	53341	1			T75	66		T76	2		T79	5
valid_sources[0x1b]	51084	1			T74	1		T75	60		T76	1
valid_sources[0x1c]	50809	1			T74	3		T75	70		T76	3
valid_sources[0x1d]	51932	1			T74	2		T75	77		T79	14
valid_sources[0x1e]	53040	1			T74	1		T75	72		T76	1
valid_sources[0x1f]	52505	1			T74	2		T75	66		T76	1
valid_sources[0x20]	51978	1			T75	67		T76	1		T78	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47735

1

T74

2

T75

66

T78

2

values[0x0]

all_enables

biggest_size

359768

1

T74

1

T75

507

T76

1

values[0x1]

all_enables

biggest_size

47277

1

T74

3

T75

53

T76

1