Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468904219	52965092	0	0
DepthKnown_A	468904219	468801567	0	0
RvalidKnown_A	468904219	468801567	0	0
WreadyKnown_A	468904219	468801567	0	0
gen_passthru_fifo.paramCheckPass	983	983	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	52965092	0	0
T1	145612	20812	0	0
T4	91760	10826	0	0
T5	536785	75601	0	0
T6	137230	18312	0	0
T17	181723	19572	0	0
T43	238796	24306	0	0
T59	210015	27372	0	0
T86	342991	42198	0	0
T87	79117	8896	0	0
T88	83364	10127	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468904219	40678567	0	0
DepthKnown_A	468904219	468801567	0	0
RvalidKnown_A	468904219	468801567	0	0
WreadyKnown_A	468904219	468801567	0	0
gen_passthru_fifo.paramCheckPass	983	983	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	40678567	0	0
T1	145612	14170	0	0
T4	91760	8463	0	0
T5	536785	68699	0	0
T6	137230	13241	0	0
T17	181723	15802	0	0
T43	238796	17968	0	0
T59	210015	24681	0	0
T86	342991	32411	0	0
T87	79117	6575	0	0
T88	83364	7436	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468904219	36780086	0	0
DepthKnown_A	468904219	468801567	0	0
RvalidKnown_A	468904219	468801567	0	0
WreadyKnown_A	468904219	468801567	0	0
gen_passthru_fifo.paramCheckPass	983	983	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	36780086	0	0
T1	145612	8195	0	0
T4	91760	6121	0	0
T5	536785	64700	0	0
T6	137230	7538	0	0
T17	181723	8118	0	0
T43	238796	13480	0	0
T59	210015	6802	0	0
T86	342991	41627	0	0
T87	79117	4572	0	0
T88	83364	6119	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468904219	32748436	0	0
DepthKnown_A	468904219	468801567	0	0
RvalidKnown_A	468904219	468801567	0	0
WreadyKnown_A	468904219	468801567	0	0
gen_passthru_fifo.paramCheckPass	983	983	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	32748436	0	0
T1	145612	7753	0	0
T4	91760	5987	0	0
T5	536785	64284	0	0
T6	137230	7270	0	0
T17	181723	7864	0	0
T43	238796	13093	0	0
T59	210015	6598	0	0
T86	342991	39019	0	0
T87	79117	4441	0	0
T88	83364	5936	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	468801567	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539447342	87657	0	0
DepthKnown_A	539447342	539332385	0	0
RvalidKnown_A	539447342	539332385	0	0
WreadyKnown_A	539447342	539332385	0	0
gen_passthru_fifo.paramCheckPass	2870	2870	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	87657	0	0
T1	145612	65	0	0
T4	91760	13	0	0
T5	536785	39	0	0
T6	137230	26	0	0
T17	181723	31	0	0
T43	238796	75	0	0
T59	210015	78	0	0
T86	342991	14	0	0
T87	79117	13	0	0
T88	83364	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2870	2870	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539447342	89498	0	0
DepthKnown_A	539447342	539332385	0	0
RvalidKnown_A	539447342	539332385	0	0
WreadyKnown_A	539447342	539332385	0	0
gen_passthru_fifo.paramCheckPass	2870	2870	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	89498	0	0
T1	145612	65	0	0
T4	91760	13	0	0
T5	536785	39	0	0
T6	137230	26	0	0
T17	181723	31	0	0
T43	238796	75	0	0
T59	210015	78	0	0
T86	342991	14	0	0
T87	79117	13	0	0
T88	83364	35	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2870	2870	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539447342	53256	0	0
DepthKnown_A	539447342	539332385	0	0
RvalidKnown_A	539447342	539332385	0	0
WreadyKnown_A	539447342	539332385	0	0
gen_passthru_fifo.paramCheckPass	2870	2870	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	53256	0	0
T1	145612	62	0	0
T4	91760	12	0	0
T5	536785	37	0	0
T6	137230	23	0	0
T17	181723	28	0	0
T43	238796	72	0	0
T59	210015	77	0	0
T86	342991	13	0	0
T87	79117	12	0	0
T88	83364	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2870	2870	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539447342	53256	0	0
DepthKnown_A	539447342	539332385	0	0
RvalidKnown_A	539447342	539332385	0	0
WreadyKnown_A	539447342	539332385	0	0
gen_passthru_fifo.paramCheckPass	2870	2870	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	53256	0	0
T1	145612	62	0	0
T4	91760	12	0	0
T5	536785	37	0	0
T6	137230	23	0	0
T17	181723	28	0	0
T43	238796	72	0	0
T59	210015	77	0	0
T86	342991	13	0	0
T87	79117	12	0	0
T88	83364	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2870	2870	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539447342	34401	0	0
DepthKnown_A	539447342	539332385	0	0
RvalidKnown_A	539447342	539332385	0	0
WreadyKnown_A	539447342	539332385	0	0
gen_passthru_fifo.paramCheckPass	2870	2870	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	34401	0	0
T1	145612	3	0	0
T4	91760	1	0	0
T5	536785	2	0	0
T6	137230	3	0	0
T17	181723	3	0	0
T43	238796	3	0	0
T59	210015	1	0	0
T86	342991	1	0	0
T87	79117	1	0	0
T88	83364	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2870	2870	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	539447342	36242	0	0
DepthKnown_A	539447342	539332385	0	0
RvalidKnown_A	539447342	539332385	0	0
WreadyKnown_A	539447342	539332385	0	0
gen_passthru_fifo.paramCheckPass	2870	2870	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	36242	0	0
T1	145612	3	0	0
T4	91760	1	0	0
T5	536785	2	0	0
T6	137230	3	0	0
T17	181723	3	0	0
T43	238796	3	0	0
T59	210015	1	0	0
T86	342991	1	0	0
T87	79117	1	0	0
T88	83364	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	539447342	539332385	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2870	2870	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0