Line Coverage for Module :
pinmux_strap_sampling
| Line No. | Total | Covered | Percent |
TOTAL | | 303 | 301 | 99.34 |
CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 1 | 1 | 100.00 |
CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
CONT_ASSIGN | 230 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
CONT_ASSIGN | 236 | 1 | 1 | 100.00 |
CONT_ASSIGN | 240 | 1 | 1 | 100.00 |
CONT_ASSIGN | 241 | 1 | 1 | 100.00 |
CONT_ASSIGN | 242 | 1 | 1 | 100.00 |
CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
ALWAYS | 262 | 9 | 9 | 100.00 |
ALWAYS | 283 | 9 | 9 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
ALWAYS | 312 | 17 | 17 | 100.00 |
CONT_ASSIGN | 371 | 1 | 1 | 100.00 |
CONT_ASSIGN | 372 | 1 | 1 | 100.00 |
CONT_ASSIGN | 373 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 396 | 1 | 1 | 100.00 |
CONT_ASSIGN | 400 | 1 | 1 | 100.00 |
CONT_ASSIGN | 401 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 404 | 1 | 1 | 100.00 |
CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 405 | 1 | 1 | 100.00 |
CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
CONT_ASSIGN | 412 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 414 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 417 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 418 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 0 | 0.00 |
CONT_ASSIGN | 419 | 1 | 0 | 0.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 419 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
CONT_ASSIGN | 420 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
132 |
1 |
1 |
133 |
1 |
1 |
153 |
1 |
1 |
157 |
1 |
1 |
187 |
1 |
1 |
230 |
1 |
1 |
232 |
1 |
1 |
236 |
1 |
1 |
240 |
1 |
1 |
241 |
1 |
1 |
242 |
1 |
1 |
259 |
1 |
1 |
262 |
1 |
1 |
263 |
1 |
1 |
264 |
1 |
1 |
268 |
1 |
1 |
269 |
1 |
1 |
|
|
|
MISSING_ELSE |
274 |
1 |
1 |
275 |
1 |
1 |
276 |
1 |
1 |
277 |
1 |
1 |
|
|
|
MISSING_ELSE |
|
|
|
MISSING_ELSE |
283 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
287 |
1 |
1 |
289 |
1 |
1 |
290 |
1 |
1 |
291 |
1 |
1 |
292 |
1 |
1 |
308 |
1 |
1 |
312 |
1 |
1 |
315 |
1 |
1 |
316 |
1 |
1 |
317 |
1 |
1 |
319 |
1 |
1 |
321 |
1 |
1 |
323 |
1 |
1 |
324 |
1 |
1 |
325 |
1 |
1 |
328 |
1 |
1 |
329 |
1 |
1 |
330 |
1 |
1 |
331 |
1 |
1 |
|
|
|
MISSING_ELSE |
335 |
1 |
1 |
336 |
1 |
1 |
337 |
1 |
1 |
338 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
371 |
1 |
1 |
372 |
1 |
1 |
373 |
1 |
1 |
396 |
5 |
5 |
400 |
1 |
1 |
401 |
1 |
1 |
404 |
4 |
4 |
405 |
4 |
4 |
412 |
2 |
2 |
414 |
3 |
3 |
417 |
58 |
58 |
418 |
58 |
58 |
419 |
56 |
58 |
420 |
58 |
58 |
Cond Coverage for Module :
pinmux_strap_sampling
| Total | Covered | Percent |
Conditions | 55 | 55 | 100.00 |
Logical | 55 | 55 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 230
EXPRESSION (lc_strap_sample_en ? in_padring_i[30] : tap_strap_q[0])
---------1--------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 232
EXPRESSION (rv_strap_sample_en ? in_padring_i[27] : tap_strap_q[1])
---------1--------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T6,T17 |
LINE 236
EXPRESSION (dft_strap_sample_en ? ({in_padring_i[42], in_padring_i[40]}) : dft_strap_q)
---------1---------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T6,T17 |
LINE 240
EXPRESSION (dft_strap_sample_en | dft_strap_valid_q)
---------1--------- --------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T4,T6,T17 |
1 | 0 | Covered | T4,T6,T17 |
LINE 268
EXPRESSION (strap_en_q && tap_sampling_en)
-----1---- -------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T17 |
1 | 0 | Covered | T5,T59,T18 |
1 | 1 | Covered | T4,T6,T17 |
LINE 274
EXPRESSION (strap_en_q || tap_sampling_en)
-----1---- -------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T43,T59 |
0 | 1 | Covered | T4,T6,T17 |
1 | 0 | Covered | T5,T59,T18 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[35])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[36])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[37])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[38])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 396
EXPRESSION (jtag_en ? 1'b0 : in_padring_i[39])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 400
EXPRESSION (jtag_en ? jtag_rsp.tdo : out_core_i[36])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 401
EXPRESSION (jtag_en ? jtag_rsp.tdo_oe : oe_core_i[36])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 404
EXPRESSION (jtag_en ? 1'b0 : out_core_i[35])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 404
EXPRESSION (jtag_en ? 1'b0 : out_core_i[37])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 404
EXPRESSION (jtag_en ? 1'b0 : out_core_i[38])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 404
EXPRESSION (jtag_en ? 1'b0 : out_core_i[39])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 405
EXPRESSION (jtag_en ? 1'b0 : oe_core_i[35])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 405
EXPRESSION (jtag_en ? 1'b0 : oe_core_i[37])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 405
EXPRESSION (jtag_en ? 1'b0 : oe_core_i[38])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 405
EXPRESSION (jtag_en ? 1'b0 : oe_core_i[39])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 412
EXPRESSION
Number Term
1 jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[38])
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 412
EXPRESSION
Number Term
1 jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[39])
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 414
EXPRESSION (jtag_en ? '0 : attr_core_i[35])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 414
EXPRESSION (jtag_en ? '0 : attr_core_i[36])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
LINE 414
EXPRESSION (jtag_en ? '0 : attr_core_i[37])
---1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T59,T44,T20 |
Branch Coverage for Module :
pinmux_strap_sampling
| Line No. | Total | Covered | Percent |
Branches |
|
59 |
58 |
98.31 |
TERNARY |
230 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
236 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
404 |
2 |
2 |
100.00 |
TERNARY |
405 |
2 |
2 |
100.00 |
TERNARY |
414 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
400 |
2 |
2 |
100.00 |
TERNARY |
401 |
2 |
2 |
100.00 |
TERNARY |
414 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
404 |
2 |
2 |
100.00 |
TERNARY |
405 |
2 |
2 |
100.00 |
TERNARY |
414 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
404 |
2 |
2 |
100.00 |
TERNARY |
405 |
2 |
2 |
100.00 |
TERNARY |
412 |
2 |
2 |
100.00 |
TERNARY |
396 |
2 |
2 |
100.00 |
TERNARY |
404 |
2 |
2 |
100.00 |
TERNARY |
405 |
2 |
2 |
100.00 |
TERNARY |
412 |
2 |
2 |
100.00 |
IF |
268 |
2 |
2 |
100.00 |
IF |
274 |
3 |
3 |
100.00 |
IF |
283 |
2 |
2 |
100.00 |
CASE |
321 |
6 |
5 |
83.33 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 230 (lc_strap_sample_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 232 (rv_strap_sample_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T17 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 236 (dft_strap_sample_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T17 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 404 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 405 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 414 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 400 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 401 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 414 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 404 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 405 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 414 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 404 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 405 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 412 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 396 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 404 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 405 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 412 (jtag_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T59,T44,T20 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 268 if ((strap_en_q && tap_sampling_en))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T17 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 274 if ((strap_en_q || tap_sampling_en))
-2-: 276 if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T4,T6,T17 |
1 |
0 |
Covered |
T4,T5,T6 |
0 |
- |
Covered |
T5,T43,T59 |
LineNo. Expression
-1-: 283 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 321 case (tap_strap)
-2-: 328 if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel]))
-3-: 335 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[DftEnTapSel]))
Branches:
-1- | -2- | -3- | Status | Tests |
LcTapSel |
- |
- |
Covered |
T59,T57,T58 |
RvTapSel |
1 |
- |
Covered |
T44,T20,T70 |
RvTapSel |
0 |
- |
Covered |
T240,T653,T403 |
DftTapSel |
- |
1 |
Covered |
T66,T67,T68 |
DftTapSel |
- |
0 |
Not Covered |
|
default |
- |
- |
Covered |
T4,T6,T17 |
Assert Coverage for Module :
pinmux_strap_sampling
Assertion Details
DftTapOff0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117267223 |
34327854 |
0 |
250 |
T1 |
48021 |
2481 |
0 |
0 |
T4 |
23361 |
2483 |
0 |
0 |
T5 |
129981 |
129579 |
0 |
2 |
T6 |
37714 |
2484 |
0 |
0 |
T17 |
46372 |
2484 |
0 |
0 |
T18 |
0 |
0 |
0 |
2 |
T20 |
0 |
0 |
0 |
2 |
T43 |
59178 |
7448 |
0 |
0 |
T57 |
0 |
0 |
0 |
2 |
T58 |
0 |
0 |
0 |
2 |
T59 |
52242 |
51791 |
0 |
2 |
T69 |
0 |
0 |
0 |
2 |
T70 |
0 |
0 |
0 |
2 |
T84 |
0 |
0 |
0 |
2 |
T86 |
127583 |
2484 |
0 |
0 |
T87 |
19832 |
2483 |
0 |
0 |
T88 |
21104 |
2484 |
0 |
0 |
T264 |
0 |
0 |
0 |
2 |
LcHwDebugEnClear_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117267223 |
11945486 |
0 |
15 |
T18 |
61908 |
1254 |
0 |
0 |
T19 |
78750 |
0 |
0 |
0 |
T20 |
275874 |
0 |
0 |
0 |
T54 |
315207 |
0 |
0 |
0 |
T57 |
0 |
4203 |
0 |
0 |
T58 |
0 |
2242 |
0 |
0 |
T63 |
63773 |
5104 |
0 |
0 |
T64 |
0 |
4982 |
0 |
0 |
T65 |
0 |
4981 |
0 |
0 |
T102 |
35566 |
0 |
0 |
0 |
T107 |
28817 |
0 |
0 |
0 |
T135 |
157221 |
0 |
0 |
0 |
T149 |
0 |
0 |
0 |
1 |
T150 |
0 |
0 |
0 |
1 |
T162 |
0 |
0 |
0 |
1 |
T163 |
0 |
0 |
0 |
1 |
T164 |
0 |
0 |
0 |
1 |
T171 |
0 |
5103 |
0 |
0 |
T250 |
0 |
24663 |
0 |
0 |
T261 |
0 |
0 |
0 |
1 |
T262 |
0 |
0 |
0 |
1 |
T263 |
0 |
0 |
0 |
1 |
T267 |
0 |
0 |
0 |
1 |
T291 |
0 |
5101 |
0 |
0 |
T387 |
42422 |
0 |
0 |
0 |
T505 |
0 |
5102 |
0 |
0 |
T646 |
20426 |
0 |
0 |
0 |
T654 |
0 |
0 |
0 |
1 |
LcHwDebugEnSetRev0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117267223 |
1425 |
0 |
85 |
T1 |
48021 |
1 |
0 |
0 |
T4 |
23361 |
1 |
0 |
0 |
T5 |
129981 |
0 |
0 |
1 |
T6 |
37714 |
1 |
0 |
0 |
T17 |
46372 |
1 |
0 |
0 |
T20 |
0 |
0 |
0 |
1 |
T43 |
59178 |
3 |
0 |
0 |
T56 |
0 |
0 |
0 |
1 |
T58 |
0 |
0 |
0 |
1 |
T59 |
52242 |
1 |
0 |
0 |
T84 |
0 |
0 |
0 |
1 |
T86 |
127583 |
1 |
0 |
0 |
T87 |
19832 |
1 |
0 |
0 |
T88 |
21104 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T149 |
0 |
0 |
0 |
1 |
T150 |
0 |
0 |
0 |
1 |
T159 |
0 |
0 |
0 |
1 |
T162 |
0 |
0 |
0 |
1 |
T264 |
0 |
0 |
0 |
1 |
LcHwDebugEnSetRev1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117267223 |
1425 |
0 |
85 |
T1 |
48021 |
1 |
0 |
0 |
T4 |
23361 |
1 |
0 |
0 |
T5 |
129981 |
0 |
0 |
1 |
T6 |
37714 |
1 |
0 |
0 |
T17 |
46372 |
1 |
0 |
0 |
T20 |
0 |
0 |
0 |
1 |
T43 |
59178 |
3 |
0 |
0 |
T56 |
0 |
0 |
0 |
1 |
T58 |
0 |
0 |
0 |
1 |
T59 |
52242 |
1 |
0 |
0 |
T84 |
0 |
0 |
0 |
1 |
T86 |
127583 |
1 |
0 |
0 |
T87 |
19832 |
1 |
0 |
0 |
T88 |
21104 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
T149 |
0 |
0 |
0 |
1 |
T150 |
0 |
0 |
0 |
1 |
T159 |
0 |
0 |
0 |
1 |
T162 |
0 |
0 |
0 |
1 |
T264 |
0 |
0 |
0 |
1 |
LcHwDebugEnSet_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117267223 |
1425 |
0 |
0 |
T1 |
48021 |
1 |
0 |
0 |
T4 |
23361 |
1 |
0 |
0 |
T5 |
129981 |
0 |
0 |
0 |
T6 |
37714 |
1 |
0 |
0 |
T17 |
46372 |
1 |
0 |
0 |
T43 |
59178 |
3 |
0 |
0 |
T59 |
52242 |
1 |
0 |
0 |
T86 |
127583 |
1 |
0 |
0 |
T87 |
19832 |
1 |
0 |
0 |
T88 |
21104 |
1 |
0 |
0 |
T99 |
0 |
1 |
0 |
0 |
RvTapOff0_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117267223 |
239 |
0 |
170 |
T1 |
48021 |
0 |
0 |
0 |
T5 |
129981 |
2 |
0 |
2 |
T6 |
37714 |
0 |
0 |
0 |
T17 |
46372 |
0 |
0 |
0 |
T20 |
0 |
0 |
0 |
2 |
T43 |
59178 |
0 |
0 |
0 |
T56 |
0 |
0 |
0 |
2 |
T57 |
0 |
2 |
0 |
0 |
T58 |
0 |
3 |
0 |
2 |
T59 |
52242 |
0 |
0 |
0 |
T69 |
0 |
1 |
0 |
0 |
T84 |
0 |
3 |
0 |
2 |
T86 |
127583 |
0 |
0 |
0 |
T87 |
19832 |
0 |
0 |
0 |
T88 |
21104 |
0 |
0 |
0 |
T99 |
41414 |
0 |
0 |
0 |
T149 |
0 |
1 |
0 |
2 |
T150 |
0 |
0 |
0 |
2 |
T155 |
0 |
1 |
0 |
0 |
T159 |
0 |
11 |
0 |
2 |
T162 |
0 |
1 |
0 |
2 |
T264 |
0 |
1 |
0 |
2 |
RvTapOff1_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117267223 |
33214023 |
0 |
0 |
T1 |
48021 |
2767 |
0 |
0 |
T4 |
23361 |
3302 |
0 |
0 |
T5 |
129981 |
129583 |
0 |
0 |
T6 |
37714 |
2987 |
0 |
0 |
T17 |
46372 |
2932 |
0 |
0 |
T43 |
59178 |
8128 |
0 |
0 |
T59 |
52242 |
2872 |
0 |
0 |
T86 |
127583 |
2860 |
0 |
0 |
T87 |
19832 |
2989 |
0 |
0 |
T88 |
21104 |
3106 |
0 |
0 |
TapStrapKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
117267223 |
116607831 |
0 |
0 |
T1 |
48021 |
47632 |
0 |
0 |
T4 |
23361 |
22390 |
0 |
0 |
T5 |
129981 |
129583 |
0 |
0 |
T6 |
37714 |
37192 |
0 |
0 |
T17 |
46372 |
45862 |
0 |
0 |
T43 |
59178 |
58439 |
0 |
0 |
T59 |
52242 |
51793 |
0 |
0 |
T86 |
127583 |
127119 |
0 |
0 |
T87 |
19832 |
19355 |
0 |
0 |
T88 |
21104 |
20375 |
0 |
0 |
dft_strap0_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |
dft_strap1_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |
tap_strap0_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |
tap_strap1_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |
tck_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |
tdi_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |
tdo_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |
tms_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |
trst_idxRange_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
983 |
983 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T17 |
1 |
1 |
0 |
0 |
T43 |
1 |
1 |
0 |
0 |
T59 |
1 |
1 |
0 |
0 |
T86 |
1 |
1 |
0 |
0 |
T87 |
1 |
1 |
0 |
0 |
T88 |
1 |
1 |
0 |
0 |