Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T74,T75,T78	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T74,T76,T244	Yes	T74,T76,T244	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T44,T65,T171	Yes	T44,T65,T171	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T44,T65,T171	Yes	T44,T65,T171	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T20,T71,T77	Yes	T20,T71,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T77,T188,T74	Yes	T77,T188,T74	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T77,T188,T74	Yes	T77,T188,T74	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T43,T44,T63	Yes	T43,T44,T63	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T43,T44,T18	Yes	T4,T6,T17	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T44,T20,T184	Yes	T44,T20,T184	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T43,T44,T18	Yes	T4,T6,T17	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T43,T44,T18	Yes	T4,T6,T17	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T44,T20,T70	Yes	T44,T20,T70	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T43,T44,T18	Yes	T4,T6,T17	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T44,T20,T70	Yes	T44,T20,T70	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T44,T20,T184	Yes	T44,T20,T184	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T20,T70,T184	Yes	T20,T70,T184	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T44,T20,T184	Yes	T44,T20,T184	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T44,*T20,*T70	Yes	T44,T20,T70	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T44,T20,T70	Yes	T44,T20,T70	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T74,T75,T78	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T78	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T74,T75,T79	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T44,*T70,*T253	Yes	T44,T70,T253	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T6,T17	Yes	T43,T44,T18	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T43,T44,T18	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T44,*T70,*T253	Yes	T44,T70,T253	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T17	Yes	T43,T44,T18	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T44,T70,T253	Yes	T44,T70,T253	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T264,T60,T390	Yes	T264,T60,T390	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T264,T60,T390	Yes	T264,T60,T390	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T264,T60,T390	Yes	T264,T60,T390	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T74,*T76,*T79	Yes	T74,T76,T79	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T264,T60,T390	Yes	T264,T60,T390	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T264,T60,T390	Yes	T264,T60,T390	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T264,T265,T391	Yes	T264,T265,T391	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T76,T79	Yes	T60,T61,T62	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T264,T265,T391	Yes	T264,T60,T265	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T74,*T76,*T79	Yes	T74,T76,T79	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T264,*T390,*T392	Yes	T264,T390,T392	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T264,T60,T390	Yes	T264,T60,T390	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T44,*T20,*T70	Yes	T44,T20,T70	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T20,T71,T77	Yes	T20,T71,T77	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T65,T171,T505	Yes	T65,T171,T505	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T44,*T20,*T71	Yes	T44,T20,T70	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T188,*T189,*T74	Yes	T188,T189,T74	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T24,T185,T186	Yes	T24,T185,T186	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T140,T24,T25	Yes	T140,T24,T25	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T24,T380	Yes	T140,T60,T24	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T140,T24,T25	Yes	T140,T24,T25	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T188,*T189,*T74	Yes	T188,T189,T74	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T140,*T24,*T380	Yes	T140,T24,T380	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T140,T60,T24	Yes	T140,T60,T24	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T140,T60,T380	Yes	T140,T60,T380	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T140,T60,T141	Yes	T140,T60,T141	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T140,T60,T380	Yes	T140,T60,T380	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T140,T60,T380	Yes	T140,T60,T380	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T140,T60,T141	Yes	T140,T60,T141	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T140,T60,T380	Yes	T140,T60,T380	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T188,*T189,*T74	Yes	T188,T189,T74	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T140,T60,T380	Yes	T140,T60,T380	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T140,T60,T380	Yes	T140,T60,T380	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T140,T141,T142	Yes	T140,T141,T142	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T140,T380,T141	Yes	T140,T60,T380	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T140,T141,T142	Yes	T140,T141,T142	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T188,*T189,*T74	Yes	T188,T189,T74	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T140,*T380,*T141	Yes	T140,T380,T141	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T140,T60,T380	Yes	T140,T60,T380	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T74,*T76,*T78	Yes	T74,T76,T78	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	INPUT
tl_usbdev_i.d_error	Yes	Yes	T74,T76,T79	Yes	T74,T76,T78	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T296	Yes	T29,T30,T296	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T296	Yes	T29,T30,T296	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T1,T29,T30	Yes	T29,T30,T296	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T76,T79	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T74,*T76,*T79	Yes	T74,T76,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T75,T76	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T1,*T29,*T30	Yes	T29,T30,T296	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T1,T29,T30	Yes	T1,T29,T30	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T43,T44	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T5,T43,T86	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T74,T76,T78	Yes	T74,T76,T79	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T71,T74,T76	Yes	T71,T74,T76	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T71,T74,T75	Yes	T71,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T71,T74,T76	Yes	T71,T74,T76	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T78	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T71,T74,T76	Yes	T71,T74,T76	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T43,T44	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_hmac_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T71,*T74,*T75	Yes	T71,T74,T75	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T311,T331,T679	Yes	T311,T331,T679	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	INPUT
tl_hmac_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	INPUT
tl_hmac_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T71,*T74,*T75	Yes	T71,T74,T75	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T54,*T55,*T311	Yes	T54,T55,T311	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T54,T55,T311	Yes	T54,T55,T311	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T101,T107,T388	Yes	T101,T107,T388	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	INPUT
tl_kmac_i.d_error	Yes	Yes	T74,T76,T80	Yes	T74,T76,T80	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T5,T101,T18	Yes	T101,T18,T107	INPUT
tl_kmac_i.d_sink	Yes	Yes	T74,T76,T78	Yes	T74,T76,T79	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T79	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T5,*T101,*T18	Yes	T101,T18,T107	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T5,T101,T18	Yes	T5,T101,T18	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T43,T87	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T87,T289,T60	Yes	T87,T289,T60	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T87,T289,T60	Yes	T87,T289,T60	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T87,T289,T239	Yes	T87,T289,T239	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T87,T289,T60	Yes	T87,T289,T60	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T87,T289,T239	Yes	T87,T289,T239	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T74,*T76,*T78	Yes	T74,T76,T78	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T87,T289,T239	Yes	T87,T289,T239	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T87,T289,T239	Yes	T87,T289,T239	INPUT
tl_aes_i.d_error	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T87,T289,T239	Yes	T87,T289,T239	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T87,T289,T677	Yes	T87,T289,T60	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T87,T289,T239	Yes	T87,T289,T239	INPUT
tl_aes_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T76,T78	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T74,*T76,*T78	Yes	T74,T76,T78	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T76,T78	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T87,*T289,*T239	Yes	T87,T289,T239	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T87,T289,T239	Yes	T87,T289,T239	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T5,*T18,*T104	Yes	T5,T18,T54	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T5,T18,T646	Yes	T5,T18,T646	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T5,T18,T646	Yes	T5,T18,T646	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T5,*T18,*T646	Yes	T5,T18,T646	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T71,*T74,*T75	Yes	T71,T74,T75	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T71,*T74,*T75	Yes	T71,T74,T75	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T5,*T18,*T104	Yes	T5,T18,T104	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T71,*T74,*T75	Yes	T71,T74,T75	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	INPUT
tl_edn1_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	INPUT
tl_edn1_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T71,*T74,*T75	Yes	T71,T74,T75	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T5,*T18,*T104	Yes	T5,T18,T104	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T5,T18,T104	Yes	T5,T18,T104	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T188,*T189,*T74	Yes	T188,T189,T74	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T188,*T189,*T74	Yes	T188,T189,T74	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T78	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T17	Yes	T4,T6,T17	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_otbn_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T20,*T77,*T190	Yes	T20,T77,T190	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	INPUT
tl_otbn_i.d_error	Yes	Yes	T74,T78,T79	Yes	T74,T78,T79	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	INPUT
tl_otbn_i.d_sink	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T20,*T77,*T190	Yes	T20,T77,T190	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T78,T79	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T20,*T54,*T55	Yes	T20,T54,T55	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T20,T54,T55	Yes	T20,T54,T55	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T76	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	INPUT
tl_keymgr_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T76,T78	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T5,T55,T155	Yes	T5,T55,T155	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T76,T78	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T71,*T74,*T76	Yes	T71,T74,T75	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T74,T76,T78	Yes	T74,T76,T78	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T5,*T54,*T55	Yes	T5,T54,T55	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T5,T54,T55	Yes	T5,T54,T55	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T6,T17,T1	Yes	T6,T17,T1	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T6,T17,T1	Yes	T6,T17,T1	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T74,*T75,*T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T54,T55,T70	Yes	T54,T55,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T54,T55,T70	Yes	T54,T55,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T54,T55,T70	Yes	T54,T55,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T54,T55,T56	Yes	T54,T55,T56	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T54,T55,T70	Yes	T54,T55,T70	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T188,*T189,*T418	Yes	T188,T189,T418	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T54,T55,T70	Yes	T54,T55,T70	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T54,T55,T70	Yes	T54,T55,T70	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T74,T76,T80	Yes	T74,T76,T80	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T169,T292,T188	Yes	T169,T292,T188	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T109,T165,T166	Yes	T54,T55,T70	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T109,T165,T166	Yes	T54,T55,T70	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T188,*T189,*T74	Yes	T188,T189,T418	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T74,T76,T79	Yes	T74,T76,T79	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T109,*T165,*T166	Yes	T109,T165,T166	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T54,T55,T70	Yes	T54,T55,T70	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T43,T44	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T74,T75,T76	Yes	T74,T75,T76	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range