Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T168,T286,T287
0	1	Covered	T168,T286,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T168,T286,T287
1	Covered	T168,T286,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T168,T286,T287
1	Covered	T168,T286,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T286,T287
1	1	Covered	T168,T286,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T168,T286,T287
1	0	Covered	T168,T286,T287
1	1	Covered	T168,T286,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T168,T286,T287

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T168,T286,T287
0	Covered	T168,T286,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T168,T286,T287
0	Covered	T168,T286,T287

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	937808438	921973544	0	0
CheckNGreaterZero_A	1966	1966	0	0
GntImpliesReady_A	937808438	8371	0	0
GntImpliesValid_A	937808438	8371	0	0
GrantKnown_A	937808438	921973544	0	0
IdxKnown_A	937808438	921973544	0	0
IndexIsCorrect_A	937808438	8371	0	0
NoReadyValidNoGrant_A	937808438	0	0	0
Priority_A	937808438	8371	0	0
ReadyAndValidImplyGrant_A	937808438	8371	0	0
ReqAndReadyImplyGrant_A	937808438	8371	0	0
ReqImpliesValid_A	937808438	8371	0	0
ValidKnown_A	937808438	921973544	0	0
gen_data_port_assertion.DataFlow_A	937808438	8371	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	921973544	0	0
T1	291224	291122	0	0
T4	183520	183404	0	0
T5	1073570	1073366	0	0
T6	274460	274344	0	0
T17	363446	363322	0	0
T43	477592	477258	0	0
T59	420030	419906	0	0
T86	685982	685866	0	0
T87	158234	158110	0	0
T88	166728	166612	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1966	1966	0	0
T1	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T43	2	2	0	0
T59	2	2	0	0
T86	2	2	0	0
T87	2	2	0	0
T88	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	8371	0	0
T15	262962	0	0	0
T168	221218	2797	0	0
T204	446550	0	0	0
T211	369700	0	0	0
T217	564198	0	0	0
T286	0	2784	0	0
T287	0	2790	0	0
T332	403058	0	0	0
T376	266224	0	0	0
T377	539244	0	0	0
T378	175040	0	0	0
T379	318190	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	8371	0	0
T15	262962	0	0	0
T168	221218	2797	0	0
T204	446550	0	0	0
T211	369700	0	0	0
T217	564198	0	0	0
T286	0	2784	0	0
T287	0	2790	0	0
T332	403058	0	0	0
T376	266224	0	0	0
T377	539244	0	0	0
T378	175040	0	0	0
T379	318190	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	921973544	0	0
T1	291224	291122	0	0
T4	183520	183404	0	0
T5	1073570	1073366	0	0
T6	274460	274344	0	0
T17	363446	363322	0	0
T43	477592	477258	0	0
T59	420030	419906	0	0
T86	685982	685866	0	0
T87	158234	158110	0	0
T88	166728	166612	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	921973544	0	0
T1	291224	291122	0	0
T4	183520	183404	0	0
T5	1073570	1073366	0	0
T6	274460	274344	0	0
T17	363446	363322	0	0
T43	477592	477258	0	0
T59	420030	419906	0	0
T86	685982	685866	0	0
T87	158234	158110	0	0
T88	166728	166612	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	8371	0	0
T15	262962	0	0	0
T168	221218	2797	0	0
T204	446550	0	0	0
T211	369700	0	0	0
T217	564198	0	0	0
T286	0	2784	0	0
T287	0	2790	0	0
T332	403058	0	0	0
T376	266224	0	0	0
T377	539244	0	0	0
T378	175040	0	0	0
T379	318190	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	8371	0	0
T15	262962	0	0	0
T168	221218	2797	0	0
T204	446550	0	0	0
T211	369700	0	0	0
T217	564198	0	0	0
T286	0	2784	0	0
T287	0	2790	0	0
T332	403058	0	0	0
T376	266224	0	0	0
T377	539244	0	0	0
T378	175040	0	0	0
T379	318190	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	8371	0	0
T15	262962	0	0	0
T168	221218	2797	0	0
T204	446550	0	0	0
T211	369700	0	0	0
T217	564198	0	0	0
T286	0	2784	0	0
T287	0	2790	0	0
T332	403058	0	0	0
T376	266224	0	0	0
T377	539244	0	0	0
T378	175040	0	0	0
T379	318190	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	8371	0	0
T15	262962	0	0	0
T168	221218	2797	0	0
T204	446550	0	0	0
T211	369700	0	0	0
T217	564198	0	0	0
T286	0	2784	0	0
T287	0	2790	0	0
T332	403058	0	0	0
T376	266224	0	0	0
T377	539244	0	0	0
T378	175040	0	0	0
T379	318190	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	8371	0	0
T15	262962	0	0	0
T168	221218	2797	0	0
T204	446550	0	0	0
T211	369700	0	0	0
T217	564198	0	0	0
T286	0	2784	0	0
T287	0	2790	0	0
T332	403058	0	0	0
T376	266224	0	0	0
T377	539244	0	0	0
T378	175040	0	0	0
T379	318190	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	921973544	0	0
T1	291224	291122	0	0
T4	183520	183404	0	0
T5	1073570	1073366	0	0
T6	274460	274344	0	0
T17	363446	363322	0	0
T43	477592	477258	0	0
T59	420030	419906	0	0
T86	685982	685866	0	0
T87	158234	158110	0	0
T88	166728	166612	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	937808438	8371	0	0
T15	262962	0	0	0
T168	221218	2797	0	0
T204	446550	0	0	0
T211	369700	0	0	0
T217	564198	0	0	0
T286	0	2784	0	0
T287	0	2790	0	0
T332	403058	0	0	0
T376	266224	0	0	0
T377	539244	0	0	0
T378	175040	0	0	0
T379	318190	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T168,T286,T287
0	1	Covered	T168,T286,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T168,T286,T287
1	Covered	T168,T286,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T168,T286,T287
1	Covered	T168,T286,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T286,T287
1	1	Covered	T168,T286,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T168,T286,T287
1	0	Covered	T168,T286,T287
1	1	Covered	T168,T286,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T168,T286,T287

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T168,T286,T287
0	Covered	T168,T286,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T168,T286,T287
0	Covered	T168,T286,T287

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	468904219	460986772	0	0
CheckNGreaterZero_A	983	983	0	0
GntImpliesReady_A	468904219	5182	0	0
GntImpliesValid_A	468904219	5182	0	0
GrantKnown_A	468904219	460986772	0	0
IdxKnown_A	468904219	460986772	0	0
IndexIsCorrect_A	468904219	5182	0	0
NoReadyValidNoGrant_A	468904219	0	0	0
Priority_A	468904219	5182	0	0
ReadyAndValidImplyGrant_A	468904219	5182	0	0
ReqAndReadyImplyGrant_A	468904219	5182	0	0
ReqImpliesValid_A	468904219	5182	0	0
ValidKnown_A	468904219	460986772	0	0
gen_data_port_assertion.DataFlow_A	468904219	5182	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	460986772	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	5182	0	0
T15	131481	0	0	0
T168	110609	1734	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1720	0	0
T287	0	1728	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	5182	0	0
T15	131481	0	0	0
T168	110609	1734	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1720	0	0
T287	0	1728	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	460986772	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	460986772	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	5182	0	0
T15	131481	0	0	0
T168	110609	1734	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1720	0	0
T287	0	1728	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	5182	0	0
T15	131481	0	0	0
T168	110609	1734	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1720	0	0
T287	0	1728	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	5182	0	0
T15	131481	0	0	0
T168	110609	1734	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1720	0	0
T287	0	1728	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	5182	0	0
T15	131481	0	0	0
T168	110609	1734	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1720	0	0
T287	0	1728	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	5182	0	0
T15	131481	0	0	0
T168	110609	1734	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1720	0	0
T287	0	1728	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	460986772	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	5182	0	0
T15	131481	0	0	0
T168	110609	1734	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1720	0	0
T287	0	1728	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T168,T286,T287
0	1	Covered	T168,T286,T287
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T168,T286,T287
1	Covered	T168,T286,T287

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T168,T286,T287
1	Covered	T168,T286,T287

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T286,T287
1	1	Covered	T168,T286,T287

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T168,T286,T287
1	0	Covered	T168,T286,T287
1	1	Covered	T168,T286,T287

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T168,T286,T287

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T168,T286,T287
0	Covered	T168,T286,T287

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T168,T286,T287
0	Covered	T168,T286,T287

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	468904219	460986772	0	0
CheckNGreaterZero_A	983	983	0	0
GntImpliesReady_A	468904219	3189	0	0
GntImpliesValid_A	468904219	3189	0	0
GrantKnown_A	468904219	460986772	0	0
IdxKnown_A	468904219	460986772	0	0
IndexIsCorrect_A	468904219	3189	0	0
NoReadyValidNoGrant_A	468904219	0	0	0
Priority_A	468904219	3189	0	0
ReadyAndValidImplyGrant_A	468904219	3189	0	0
ReqAndReadyImplyGrant_A	468904219	3189	0	0
ReqImpliesValid_A	468904219	3189	0	0
ValidKnown_A	468904219	460986772	0	0
gen_data_port_assertion.DataFlow_A	468904219	3189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	460986772	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	983	983	0	0
T1	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T43	1	1	0	0
T59	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	3189	0	0
T15	131481	0	0	0
T168	110609	1063	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1064	0	0
T287	0	1062	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	3189	0	0
T15	131481	0	0	0
T168	110609	1063	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1064	0	0
T287	0	1062	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	460986772	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	460986772	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	3189	0	0
T15	131481	0	0	0
T168	110609	1063	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1064	0	0
T287	0	1062	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	3189	0	0
T15	131481	0	0	0
T168	110609	1063	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1064	0	0
T287	0	1062	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	3189	0	0
T15	131481	0	0	0
T168	110609	1063	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1064	0	0
T287	0	1062	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	3189	0	0
T15	131481	0	0	0
T168	110609	1063	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1064	0	0
T287	0	1062	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	3189	0	0
T15	131481	0	0	0
T168	110609	1063	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1064	0	0
T287	0	1062	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	460986772	0	0
T1	145612	145561	0	0
T4	91760	91702	0	0
T5	536785	536683	0	0
T6	137230	137172	0	0
T17	181723	181661	0	0
T43	238796	238629	0	0
T59	210015	209953	0	0
T86	342991	342933	0	0
T87	79117	79055	0	0
T88	83364	83306	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468904219	3189	0	0
T15	131481	0	0	0
T168	110609	1063	0	0
T204	223275	0	0	0
T211	184850	0	0	0
T217	282099	0	0	0
T286	0	1064	0	0
T287	0	1062	0	0
T332	201529	0	0	0
T376	133112	0	0	0
T377	269622	0	0	0
T378	87520	0	0	0
T379	159095	0	0	0