Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3753320	1			T76	104		T77	95		T78	258
values[2]	766090	1			T76	52		T77	36		T78	49
values[3]	110706	1			T77	1		T78	1		T82	18
values[4]	57446	1			T82	18		T423	454		T435	5
values[5]	38371	1			T82	18		T423	337		T435	4
values[6]	28168	1			T82	18		T423	218		T435	4
values[7]	23130	1			T82	19		T423	176		T435	4
values[8]	19929	1			T82	18		T423	105		T435	4
values[9]	17648	1			T82	18		T423	66		T435	4
values[10]	15990	1			T82	18		T423	51		T435	4
values[11]	14641	1			T82	18		T423	41		T435	4
values[12]	13356	1			T82	19		T423	35		T435	4
values[13]	12956	1			T82	18		T423	28		T435	4
values[14]	12554	1			T82	19		T423	20		T435	4
values[15]	12171	1			T82	19		T423	27		T435	4
values[16]	11578	1			T82	19		T423	24		T435	4
values[17]	11237	1			T82	18		T423	27		T435	4
values[18]	10700	1			T82	18		T423	20		T435	4
values[19]	10518	1			T82	18		T423	23		T435	4
values[20]	10142	1			T82	18		T423	21		T435	4
values[21]	9832	1			T82	18		T423	22		T435	4
values[22]	9283	1			T82	18		T423	30		T435	4
values[23]	9048	1			T82	19		T423	26		T435	4
values[24]	8603	1			T82	18		T423	27		T435	4
values[25]	7926	1			T82	18		T423	35		T435	4
values[26]	7705	1			T82	18		T423	35		T675	2
values[27]	7761	1			T82	19		T423	35		T675	1
values[28]	7342	1			T82	18		T423	20		T675	3
values[29]	7033	1			T82	18		T423	25		T675	3
values[30]	6448	1			T82	18		T423	17		T675	2
values[31]	5904	1			T82	18		T423	19		T675	3
values[32]	5470	1			T82	18		T423	15		T675	2
values[33]	5198	1			T82	18		T423	19		T675	1
values[34]	4706	1			T82	19		T423	27		T675	4
values[35]	4358	1			T82	18		T423	24		T675	1
values[36]	4226	1			T82	18		T423	18		T675	2
values[37]	3930	1			T82	18		T423	18		T675	1
values[38]	3719	1			T82	18		T423	11		T675	1
values[39]	3673	1			T82	18		T423	15		T675	2
values[40]	3526	1			T82	19		T423	25		T675	1
values[41]	3346	1			T82	19		T423	34		T675	2
values[42]	3316	1			T82	18		T423	37		T675	6
values[43]	3237	1			T82	18		T423	25		T675	1
values[44]	3231	1			T82	19		T423	29		T675	2
values[45]	3142	1			T82	18		T423	26		T675	5
values[46]	3128	1			T82	18		T423	18		T675	2
values[47]	2938	1			T82	19		T423	9		T675	1
values[48]	3010	1			T82	19		T423	17		T675	2
values[49]	2937	1			T82	18		T423	22		T675	1
values[50]	2900	1			T82	18		T423	21		T675	1
values[51]	2878	1			T82	19		T423	22		T675	4
values[52]	2740	1			T82	18		T423	16		T675	2
values[53]	2756	1			T82	19		T423	15		T675	2
values[54]	2703	1			T82	18		T423	12		T675	4
values[55]	2616	1			T82	18		T423	12		T675	3
values[56]	2650	1			T82	18		T423	22		T675	1
values[57]	2500	1			T82	18		T423	22		T675	1
values[58]	2488	1			T82	18		T423	27		T675	1
values[59]	2525	1			T82	18		T423	20		T675	4
values[60]	2516	1			T82	18		T423	17		T675	2
values[61]	2682	1			T82	18		T423	20		T675	1
values[62]	4134	1			T82	18		T423	22		T675	11
values[63]	11271	1			T82	20		T423	71		T675	40
values[64]	242652	1			T82	3459		T423	181		T675	68

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4802218	1			T76	99		T77	111		T78	202
values[2]	826837	1			T76	17		T77	30		T78	51
values[3]	87803	1			T76	3		T77	8		T78	2
values[4]	15902	1			T82	82		T225	1		T256	5
values[5]	6319	1			T82	22		T256	1		T423	55
values[6]	3799	1			T82	9		T423	37		T435	2
values[7]	2680	1			T82	2		T423	27		T435	2
values[8]	2232	1			T82	2		T423	12		T435	2
values[9]	2004	1			T82	2		T423	15		T435	2
values[10]	1805	1			T82	2		T423	15		T435	2
values[11]	1723	1			T82	2		T423	12		T435	2
values[12]	1567	1			T82	2		T423	14		T435	2
values[13]	1549	1			T82	2		T423	14		T435	2
values[14]	1445	1			T82	2		T423	6		T435	2
values[15]	1282	1			T82	2		T423	2		T435	2
values[16]	1238	1			T82	2		T423	2		T435	3
values[17]	1215	1			T82	2		T423	2		T435	2
values[18]	1184	1			T82	2		T423	2		T435	2
values[19]	1068	1			T82	2		T423	5		T435	4
values[20]	961	1			T82	2		T423	8		T435	2
values[21]	904	1			T82	2		T423	3		T435	2
values[22]	868	1			T82	2		T423	1		T435	2
values[23]	841	1			T82	2		T423	1		T435	2
values[24]	792	1			T82	2		T423	1		T435	2
values[25]	795	1			T82	2		T423	2		T435	2
values[26]	760	1			T82	2		T423	1		T435	1
values[27]	704	1			T82	2		T423	1		T435	1
values[28]	661	1			T82	2		T423	2		T435	2
values[29]	607	1			T82	2		T423	4		T435	2
values[30]	632	1			T82	2		T423	2		T435	3
values[31]	652	1			T82	2		T423	4		T435	2
values[32]	601	1			T82	2		T423	1		T435	2
values[33]	530	1			T82	2		T423	1		T435	2
values[34]	525	1			T82	2		T423	1		T435	2
values[35]	522	1			T82	2		T423	1		T435	2
values[36]	553	1			T82	2		T423	1		T435	2
values[37]	456	1			T82	2		T423	1		T435	2
values[38]	436	1			T82	2		T423	1		T435	2
values[39]	488	1			T82	2		T423	1		T435	2
values[40]	491	1			T82	2		T423	1		T435	2
values[41]	481	1			T82	2		T423	1		T435	2
values[42]	477	1			T82	2		T423	1		T435	2
values[43]	456	1			T82	2		T423	4		T435	2
values[44]	419	1			T82	3		T423	1		T435	2
values[45]	389	1			T82	2		T423	2		T435	2
values[46]	410	1			T82	2		T423	3		T435	2
values[47]	402	1			T82	2		T423	4		T435	1
values[48]	401	1			T82	2		T423	2		T435	1
values[49]	382	1			T82	2		T423	3		T435	2
values[50]	377	1			T82	2		T423	2		T435	2
values[51]	367	1			T82	2		T423	1		T435	3
values[52]	382	1			T82	2		T423	1		T435	2
values[53]	374	1			T82	2		T423	1		T435	2
values[54]	343	1			T82	2		T423	2		T435	2
values[55]	397	1			T82	2		T423	6		T435	1
values[56]	340	1			T82	2		T423	7		T435	1
values[57]	348	1			T82	2		T423	2		T435	2
values[58]	321	1			T82	2		T423	3		T435	2
values[59]	326	1			T82	2		T423	1		T435	2
values[60]	317	1			T82	2		T423	2		T435	2
values[61]	370	1			T82	2		T423	2		T435	2
values[62]	625	1			T82	2		T423	6		T435	2
values[63]	2533	1			T82	3		T423	30		T435	5
values[64]	25185	1			T82	364		T423	114		T435	82

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	519785	1			T76	1		T77	1		T78	2
values[2]	2728705	1			T76	116		T77	6		T78	275
values[3]	1205599	1			T76	64		T77	179		T78	72
values[4]	150518	1			T76	1		T77	9		T78	1
values[5]	78433	1			T76	1		T77	1		T82	18
values[6]	51173	1			T82	18		T423	260		T435	9
values[7]	37332	1			T82	18		T423	194		T435	16
values[8]	29577	1			T82	18		T423	157		T435	22
values[9]	24363	1			T82	18		T423	156		T435	1
values[10]	20714	1			T82	18		T423	109		T675	55
values[11]	19037	1			T82	19		T423	78		T675	14
values[12]	17703	1			T82	18		T423	43		T675	35
values[13]	16434	1			T82	18		T423	32		T675	18
values[14]	15785	1			T82	18		T423	25		T675	16
values[15]	14960	1			T82	18		T423	22		T675	10
values[16]	14183	1			T82	18		T423	24		T675	3
values[17]	13614	1			T82	18		T423	30		T675	6
values[18]	12784	1			T82	18		T423	35		T675	1
values[19]	12168	1			T82	18		T423	28		T675	3
values[20]	11553	1			T82	18		T423	14		T675	1
values[21]	11203	1			T82	18		T423	18		T675	1
values[22]	10835	1			T82	18		T423	16		T675	1
values[23]	10558	1			T82	18		T423	19		T675	1
values[24]	9660	1			T82	18		T423	13		T675	1
values[25]	9376	1			T82	18		T423	15		T675	3
values[26]	8857	1			T82	18		T423	26		T675	6
values[27]	8574	1			T82	18		T423	14		T675	1
values[28]	8252	1			T82	18		T423	17		T675	2
values[29]	7565	1			T82	18		T423	20		T675	1
values[30]	6776	1			T82	18		T423	11		T675	1
values[31]	6401	1			T82	18		T423	12		T675	2
values[32]	6074	1			T82	18		T423	22		T675	1
values[33]	5665	1			T82	18		T423	27		T675	3
values[34]	5223	1			T82	18		T423	26		T675	1
values[35]	4883	1			T82	18		T423	32		T675	1
values[36]	4612	1			T82	18		T423	15		T675	3
values[37]	4394	1			T82	18		T423	28		T675	4
values[38]	4214	1			T82	18		T423	24		T675	1
values[39]	4041	1			T82	18		T423	23		T675	2
values[40]	3863	1			T82	19		T423	22		T675	2
values[41]	3795	1			T82	18		T423	19		T675	1
values[42]	3688	1			T82	18		T423	25		T675	1
values[43]	3454	1			T82	18		T423	10		T675	1
values[44]	3394	1			T82	18		T423	9		T675	1
values[45]	3474	1			T82	18		T423	12		T675	2
values[46]	3369	1			T82	18		T423	12		T675	1
values[47]	3263	1			T82	18		T423	18		T675	2
values[48]	3261	1			T82	19		T423	15		T675	1
values[49]	3308	1			T82	18		T423	13		T675	2
values[50]	3200	1			T82	18		T423	14		T675	1
values[51]	3100	1			T82	18		T423	16		T675	3
values[52]	3075	1			T82	18		T423	16		T675	2
values[53]	3028	1			T82	18		T423	21		T675	12
values[54]	3023	1			T82	18		T423	12		T675	11
values[55]	3028	1			T82	18		T423	15		T675	4
values[56]	2940	1			T82	18		T423	10		T675	1
values[57]	2955	1			T82	18		T423	12		T675	3
values[58]	2811	1			T82	18		T423	13		T675	1
values[59]	2799	1			T82	18		T423	10		T675	6
values[60]	2761	1			T82	19		T423	14		T675	3
values[61]	2845	1			T82	18		T423	13		T675	4
values[62]	3779	1			T82	19		T423	17		T675	6
values[63]	9283	1			T82	18		T423	91		T675	23
values[64]	234218	1			T82	3097		T423	217		T675	29