Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2296973	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32228262

1

T4

18815

T5

3412

T6

9495

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	23588732	1			T4	7182		T5	733		T6	4112
values[0x0]	9185852	1			T4	11633		T5	2679		T6	5383
values[0x1]	1750651	1			T4	287		T5	49		T6	213

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	662747	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

33862488

1

T4

19102

T5

3461

T6

9708

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16107603	1			T4	9552		T5	1731		T6	4854
valid_sources[0x01]	16107642	1			T4	9550		T5	1730		T6	4854
valid_sources[0x02]	36419	1			T9	3		T146	778		T147	816
valid_sources[0x03]	36953	1			T146	854		T147	814		T148	442
valid_sources[0x04]	37182	1			T70	2		T9	4		T146	749
valid_sources[0x05]	37043	1			T207	2		T146	822		T147	814
valid_sources[0x06]	36425	1			T70	10		T146	780		T147	798
valid_sources[0x07]	37575	1			T146	821		T147	785		T148	388
valid_sources[0x08]	39407	1			T208	2		T146	813		T147	825
valid_sources[0x09]	37085	1			T207	1		T146	807		T147	837
valid_sources[0x0a]	36993	1			T9	1		T146	837		T147	762
valid_sources[0x0b]	37763	1			T207	1		T208	2		T146	814
valid_sources[0x0c]	36641	1			T146	789		T147	766		T148	432
valid_sources[0x0d]	37262	1			T81	39		T207	4		T208	1
valid_sources[0x0e]	36645	1			T70	1		T207	4		T208	1
valid_sources[0x0f]	37288	1			T146	906		T147	801		T148	391
valid_sources[0x10]	38272	1			T207	2		T208	2		T146	817
valid_sources[0x11]	37405	1			T206	39		T207	1		T208	2
valid_sources[0x12]	36662	1			T208	1		T146	767		T147	859
valid_sources[0x13]	38178	1			T207	1		T146	834		T147	824
valid_sources[0x14]	36410	1			T9	1		T207	1		T146	794
valid_sources[0x15]	37397	1			T207	1		T146	763		T147	774
valid_sources[0x16]	36705	1			T207	1		T208	1		T146	801
valid_sources[0x17]	36609	1			T208	1		T146	819		T147	797
valid_sources[0x18]	37789	1			T9	4		T208	1		T146	810
valid_sources[0x19]	36788	1			T146	746		T147	800		T148	414
valid_sources[0x1a]	37127	1			T9	2		T207	1		T146	851
valid_sources[0x1b]	37300	1			T208	3		T146	778		T147	776
valid_sources[0x1c]	37488	1			T70	1		T9	5		T146	831
valid_sources[0x1d]	37445	1			T146	771		T147	714		T148	410
valid_sources[0x1e]	37463	1			T207	1		T208	1		T146	822
valid_sources[0x1f]	37342	1			T207	1		T208	3		T146	745
valid_sources[0x20]	36126	1			T9	1		T207	1		T208	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

22862367

1

T4

7182

T5

733

T6

4112

values[0x0]

all_enables

biggest_size

9136815

1

T4

11633

T5

2679

T6

5383

values[0x1]

all_enables

biggest_size

229080

1

T70

21

T9

22

T81

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2863250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452438

1

T76

28

T77

16

T78

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1123440	1			T76	55		T77	52		T78	1
values[0x0]	1070020	1			T76	57		T77	33		T78	1
values[0x1]	1122228	1			T76	44		T77	47		T78	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2216401	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1099287

1

T76

71

T77

41

T78

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52139	1			T77	1		T82	79		T158	30
valid_sources[0x01]	52004	1			T76	2		T77	1		T78	1
valid_sources[0x02]	51983	1			T82	66		T158	29		T423	5
valid_sources[0x03]	52670	1			T76	2		T77	1		T82	77
valid_sources[0x04]	52042	1			T76	1		T77	5		T82	61
valid_sources[0x05]	51975	1			T76	4		T82	64		T158	33
valid_sources[0x06]	51394	1			T76	2		T77	1		T82	77
valid_sources[0x07]	50678	1			T77	3		T82	69		T158	37
valid_sources[0x08]	51851	1			T76	5		T82	74		T158	29
valid_sources[0x09]	51657	1			T77	2		T82	65		T158	36
valid_sources[0x0a]	52498	1			T76	5		T77	1		T82	81
valid_sources[0x0b]	50643	1			T77	1		T82	70		T158	23
valid_sources[0x0c]	51212	1			T76	3		T82	76		T158	35
valid_sources[0x0d]	51622	1			T76	1		T77	10		T78	1
valid_sources[0x0e]	51139	1			T76	1		T77	3		T82	71
valid_sources[0x0f]	51311	1			T76	3		T77	2		T82	74
valid_sources[0x10]	52297	1			T76	1		T77	2		T82	81
valid_sources[0x11]	51492	1			T76	1		T77	3		T82	71
valid_sources[0x12]	51841	1			T76	4		T77	5		T82	65
valid_sources[0x13]	52698	1			T77	11		T82	65		T158	22
valid_sources[0x14]	50501	1			T77	4		T82	74		T158	28
valid_sources[0x15]	51590	1			T76	1		T77	1		T82	59
valid_sources[0x16]	51670	1			T76	2		T77	2		T82	77
valid_sources[0x17]	51515	1			T76	2		T77	3		T82	67
valid_sources[0x18]	51768	1			T76	4		T78	1		T82	70
valid_sources[0x19]	53508	1			T76	2		T77	3		T82	74
valid_sources[0x1a]	51370	1			T76	1		T78	1		T82	64
valid_sources[0x1b]	50566	1			T76	4		T82	63		T158	27
valid_sources[0x1c]	52057	1			T76	3		T82	79		T158	45
valid_sources[0x1d]	51363	1			T76	1		T82	72		T158	27
valid_sources[0x1e]	51403	1			T76	3		T82	74		T158	35
valid_sources[0x1f]	50892	1			T76	3		T82	71		T158	29
valid_sources[0x20]	52232	1			T76	2		T77	5		T82	66

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47445

1

T76

4

T82

51

T158

31

values[0x0]

all_enables

biggest_size

357217

1

T76

23

T77

13

T78

1

values[0x1]

all_enables

biggest_size

47776

1

T76

1

T77

3

T82

70

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3050738	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

496443

1

T76

20

T77

18

T82

628

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1213992	1			T76	43		T77	49		T78	9
values[0x0]	1117733	1			T76	39		T77	48		T82	1451
values[0x1]	1215456	1			T76	37		T77	52		T78	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2342236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1204945

1

T76

44

T77

51

T78

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55107	1			T76	5		T78	1		T82	100
valid_sources[0x01]	55310	1			T77	3		T82	76		T158	13
valid_sources[0x02]	55444	1			T76	3		T77	15		T82	47
valid_sources[0x03]	55675	1			T76	3		T82	89		T158	2
valid_sources[0x04]	55373	1			T76	7		T82	57		T158	22
valid_sources[0x05]	55896	1			T76	5		T77	1		T82	33
valid_sources[0x06]	55551	1			T77	2		T82	56		T158	34
valid_sources[0x07]	54724	1			T76	1		T77	5		T78	1
valid_sources[0x08]	54298	1			T82	99		T158	32		T225	2
valid_sources[0x09]	54585	1			T77	5		T82	69		T158	13
valid_sources[0x0a]	54140	1			T82	54		T158	5		T225	2
valid_sources[0x0b]	54895	1			T76	2		T82	72		T158	49
valid_sources[0x0c]	55089	1			T82	68		T158	42		T225	5
valid_sources[0x0d]	56071	1			T76	1		T82	64		T158	37
valid_sources[0x0e]	55115	1			T82	90		T158	18		T225	3
valid_sources[0x0f]	54880	1			T76	1		T82	55		T158	38
valid_sources[0x10]	55952	1			T76	4		T78	1		T82	50
valid_sources[0x11]	56415	1			T76	3		T77	3		T82	49
valid_sources[0x12]	56255	1			T76	1		T78	1		T82	87
valid_sources[0x13]	55500	1			T76	1		T82	77		T158	41
valid_sources[0x14]	54540	1			T77	6		T82	82		T158	5
valid_sources[0x15]	55924	1			T76	5		T77	12		T82	85
valid_sources[0x16]	56439	1			T76	2		T82	124		T158	24
valid_sources[0x17]	55065	1			T76	1		T78	1		T82	63
valid_sources[0x18]	54913	1			T77	6		T82	69		T158	49
valid_sources[0x19]	56066	1			T76	3		T82	80		T158	25
valid_sources[0x1a]	55350	1			T76	1		T82	81		T158	55
valid_sources[0x1b]	55297	1			T76	3		T77	13		T82	65
valid_sources[0x1c]	55673	1			T82	91		T158	53		T225	3
valid_sources[0x1d]	55842	1			T76	2		T82	70		T158	41
valid_sources[0x1e]	55942	1			T76	4		T78	1		T82	45
valid_sources[0x1f]	56232	1			T76	1		T78	1		T82	65
valid_sources[0x20]	55581	1			T76	3		T77	6		T82	66

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52049

1

T76

1

T77

2

T82

68

values[0x0]

all_enables

biggest_size

392203

1

T76

18

T77

16

T82

500

values[0x1]

all_enables

biggest_size

52191

1

T76

1

T82

60

T158

24

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2884521	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

454468

1

T76

16

T77

28

T82

546

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1130772	1			T76	56		T77	72		T78	6
values[0x0]	1076620	1			T76	63		T77	54		T78	2
values[0x1]	1131597	1			T76	64		T77	70		T78	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2233267	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1105722

1

T76

53

T77

85

T78

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52035	1			T76	4		T77	3		T82	75
valid_sources[0x01]	51140	1			T76	4		T77	8		T82	65
valid_sources[0x02]	52171	1			T76	3		T82	68		T158	25
valid_sources[0x03]	52702	1			T82	59		T158	33		T225	1
valid_sources[0x04]	53191	1			T76	5		T77	11		T82	69
valid_sources[0x05]	52401	1			T76	1		T77	20		T82	59
valid_sources[0x06]	51307	1			T76	9		T77	1		T82	64
valid_sources[0x07]	51656	1			T76	4		T77	6		T82	56
valid_sources[0x08]	52785	1			T76	1		T77	1		T82	67
valid_sources[0x09]	52256	1			T76	3		T77	12		T82	67
valid_sources[0x0a]	52395	1			T76	3		T77	1		T82	60
valid_sources[0x0b]	51303	1			T76	5		T78	2		T82	64
valid_sources[0x0c]	52323	1			T76	8		T77	12		T82	67
valid_sources[0x0d]	51975	1			T76	2		T77	6		T82	61
valid_sources[0x0e]	51433	1			T76	1		T77	8		T78	1
valid_sources[0x0f]	52586	1			T76	4		T82	75		T158	32
valid_sources[0x10]	51988	1			T76	3		T77	8		T78	2
valid_sources[0x11]	53339	1			T76	5		T82	67		T158	31
valid_sources[0x12]	52530	1			T76	1		T77	4		T82	64
valid_sources[0x13]	53124	1			T76	3		T82	63		T158	23
valid_sources[0x14]	50844	1			T76	9		T77	11		T82	61
valid_sources[0x15]	52941	1			T76	3		T78	1		T82	53
valid_sources[0x16]	52637	1			T76	3		T78	1		T82	72
valid_sources[0x17]	52408	1			T76	2		T82	69		T158	30
valid_sources[0x18]	51647	1			T76	3		T82	64		T158	28
valid_sources[0x19]	52235	1			T76	2		T77	5		T82	68
valid_sources[0x1a]	52085	1			T77	17		T78	1		T82	77
valid_sources[0x1b]	51669	1			T76	3		T77	3		T82	67
valid_sources[0x1c]	52520	1			T76	4		T78	1		T82	71
valid_sources[0x1d]	53452	1			T76	3		T78	1		T82	66
valid_sources[0x1e]	52754	1			T78	1		T82	62		T158	29
valid_sources[0x1f]	51725	1			T82	65		T158	25		T225	5
valid_sources[0x20]	51829	1			T76	4		T82	68		T158	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47948

1

T76

1

T77

3

T82

51

values[0x0]

all_enables

biggest_size

358872

1

T76

14

T77

21

T82

435

values[0x1]

all_enables

biggest_size

47648

1

T76

1

T77

4

T82

60