Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18			93.18

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	93.10			93.10
tb.dut.top_earlgrey.u_i2c1	93.14			93.14
tb.dut.top_earlgrey.u_i2c2	93.14			93.14

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.10			93.10

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.10			93.10

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14			93.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14			93.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14			93.14

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.14			93.14

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	54	48	88.89
Total Bits	352	328	93.18
Total Bits 0->1	176	164	93.18
Total Bits 1->0	176	164	93.18

Ports	54	48	88.89
Port Bits	352	328	93.18
Port Bits 0->1	176	164	93.18
Port Bits 1->0	176	164	93.18

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	INPUT
tl_o.a_ready	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T261,*T107,*T219	Yes	T261,T107,T219	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T367,T60,T368	Yes	T367,T60,T368	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T216,T84	Yes	T83,T216,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T216,T84	Yes	T83,T216,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T367,T60,T368	Yes	T367,T60,T368	OUTPUT
cio_scl_i	Yes	Yes	T107,T219,T221	Yes	T107,T219,T221	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T107,T219,T221	Yes	T107,T219,T221	OUTPUT
cio_sda_i	Yes	Yes	T107,T219,T221	Yes	T107,T219,T221	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T107,T219,T221	Yes	T107,T219,T221	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	OUTPUT
intr_rx_threshold_o	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	OUTPUT
intr_acq_threshold_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_rx_overflow_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_controller_halt_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_scl_interference_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_sda_interference_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_sda_unstable_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_cmd_complete_o	Yes	Yes	T261,T107,T219	Yes	T261,T107,T219	OUTPUT
intr_tx_stretch_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_tx_threshold_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_acq_stretch_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_unexp_stop_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_host_timeout_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	54	48	88.89
Total Bits	348	324	93.10
Total Bits 0->1	174	162	93.10
Total Bits 1->0	174	162	93.10

Ports	54	48	88.89
Port Bits	348	324	93.10
Port Bits 0->1	174	162	93.10
Port Bits 1->0	174	162	93.10

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T261,T107,T299	Yes	T261,T107,T299	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T261,T107,T299	Yes	T261,T107,T299	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T261,T107,T60	Yes	T261,T107,T60	INPUT
tl_o.a_ready	Yes	Yes	T261,T107,T60	Yes	T261,T107,T60	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T261,T107,T327	Yes	T261,T107,T327	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T261,T107,T299	Yes	T261,T107,T60	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T261,T107,T299	Yes	T261,T107,T60	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T82,*T158	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T261,*T107,*T299	Yes	T261,T107,T299	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T261,T107,T60	Yes	T261,T107,T60	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T368,T83	Yes	T60,T368,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T216,T84	Yes	T83,T216,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T216,T84	Yes	T83,T216,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T368,T83	Yes	T60,T368,T83	OUTPUT
cio_scl_i	Yes	Yes	T107,T327,T348	Yes	T107,T327,T348	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T107,T327,T348	Yes	T107,T327,T348	OUTPUT
cio_sda_i	Yes	Yes	T107,T327,T348	Yes	T107,T327,T348	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T107,T327,T348	Yes	T107,T327,T348	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T261,T107,T327	Yes	T261,T107,T327	OUTPUT
intr_rx_threshold_o	Yes	Yes	T261,T107,T327	Yes	T261,T107,T327	OUTPUT
intr_acq_threshold_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_rx_overflow_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_controller_halt_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_scl_interference_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_sda_interference_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_sda_unstable_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_cmd_complete_o	Yes	Yes	T261,T107,T327	Yes	T261,T107,T327	OUTPUT
intr_tx_stretch_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_tx_threshold_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_acq_stretch_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_unexp_stop_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_host_timeout_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	54	48	88.89
Total Bits	350	326	93.14
Total Bits 0->1	175	163	93.14
Total Bits 1->0	175	163	93.14

Ports	54	48	88.89
Port Bits	350	326	93.14
Port Bits 0->1	175	163	93.14
Port Bits 1->0	175	163	93.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T261,T219,T299	Yes	T261,T219,T299	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T261,T219,T299	Yes	T261,T219,T299	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T261,T219,T60	Yes	T261,T219,T60	INPUT
tl_o.a_ready	Yes	Yes	T261,T219,T60	Yes	T261,T219,T60	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T82	Yes	T77,T78,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T261,T219,T313	Yes	T261,T219,T313	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T261,T219,T299	Yes	T261,T219,T60	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T261,T219,T299	Yes	T261,T219,T60	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T78,*T82	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T82,T158	Yes	T77,T82,T158	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T261,*T219,*T299	Yes	T261,T219,T299	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T261,T219,T60	Yes	T261,T219,T60	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T367,T60,T83	Yes	T367,T60,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T216,T84	Yes	T83,T216,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T216,T84	Yes	T83,T216,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T367,T60,T83	Yes	T367,T60,T83	OUTPUT
cio_scl_i	Yes	Yes	T219,T313,T95	Yes	T219,T313,T95	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T219,T313,T369	Yes	T219,T313,T369	OUTPUT
cio_sda_i	Yes	Yes	T219,T313,T95	Yes	T219,T313,T95	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T219,T313,T95	Yes	T219,T313,T95	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T261,T219,T313	Yes	T261,T219,T313	OUTPUT
intr_rx_threshold_o	Yes	Yes	T261,T219,T313	Yes	T261,T219,T313	OUTPUT
intr_acq_threshold_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_rx_overflow_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_controller_halt_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_scl_interference_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_sda_interference_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_sda_unstable_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_cmd_complete_o	Yes	Yes	T261,T219,T313	Yes	T261,T219,T313	OUTPUT
intr_tx_stretch_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_tx_threshold_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_acq_stretch_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_unexp_stop_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_host_timeout_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	54	48	88.89
Total Bits	350	326	93.14
Total Bits 0->1	175	163	93.14
Total Bits 1->0	175	163	93.14

Ports	54	48	88.89
Port Bits	350	326	93.14
Port Bits 0->1	175	163	93.14
Port Bits 1->0	175	163	93.14

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T4,T17,T44	Yes	T4,T5,T6	INPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T261,T221,T299	Yes	T261,T221,T299	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T261,T221,T299	Yes	T261,T221,T299	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T79,*T80	Yes	T70,T79,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T70,T9,T81	Yes	T70,T9,T81	INPUT
tl_i.a_valid	Yes	Yes	T261,T221,T60	Yes	T261,T221,T60	INPUT
tl_o.a_ready	Yes	Yes	T261,T221,T60	Yes	T261,T221,T60	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T261,T221,T311	Yes	T261,T221,T311	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T261,T221,T299	Yes	T261,T221,T60	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T261,T221,T299	Yes	T261,T221,T60	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T78,*T158	Yes	T76,T77,T158	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T158	Yes	T77,T78,T158	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T261,*T221,*T299	Yes	T261,T221,T299	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T261,T221,T60	Yes	T261,T221,T60	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T60,T83,T216	Yes	T60,T83,T216	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T216,T84	Yes	T83,T216,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T216,T84	Yes	T83,T216,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T60,T83,T216	Yes	T60,T83,T216	OUTPUT
cio_scl_i	Yes	Yes	T221,T321,T370	Yes	T221,T321,T370	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T221,T321,T370	Yes	T221,T321,T370	OUTPUT
cio_sda_i	Yes	Yes	T221,T321,T370	Yes	T221,T321,T370	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T221,T321,T370	Yes	T221,T321,T370	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T261,T221,T311	Yes	T261,T221,T311	OUTPUT
intr_rx_threshold_o	Yes	Yes	T261,T221,T311	Yes	T261,T221,T311	OUTPUT
intr_acq_threshold_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_rx_overflow_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_controller_halt_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_scl_interference_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_sda_interference_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_sda_unstable_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_cmd_complete_o	Yes	Yes	T261,T221,T311	Yes	T261,T221,T311	OUTPUT
intr_tx_stretch_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_tx_threshold_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_acq_stretch_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_unexp_stop_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT
intr_host_timeout_o	Yes	Yes	T261,T311,T312	Yes	T261,T311,T312	OUTPUT

*Tests covering at least one bit in the range