Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	475564269	52891271	0	0
DepthKnown_A	475564269	475461107	0	0
RvalidKnown_A	475564269	475461107	0	0
WreadyKnown_A	475564269	475461107	0	0
gen_passthru_fifo.paramCheckPass	986	986	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	52891271	0	0
T4	406694	50123	0	0
T5	72662	7515	0	0
T6	102091	12856	0	0
T17	220029	28832	0	0
T18	230779	30165	0	0
T34	161920	11850	0	0
T44	158702	12305	0	0
T55	134872	146668	0	0
T64	206408	19662	0	0
T87	466900	65728	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	986	986	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	475564269	40873202	0	0
DepthKnown_A	475564269	475461107	0	0
RvalidKnown_A	475564269	475461107	0	0
WreadyKnown_A	475564269	475461107	0	0
gen_passthru_fifo.paramCheckPass	986	986	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	40873202	0	0
T4	406694	38688	0	0
T5	72662	5404	0	0
T6	102091	9737	0	0
T17	220029	19278	0	0
T18	230779	20622	0	0
T34	161920	9190	0	0
T44	158702	8560	0	0
T55	134872	127766	0	0
T64	206408	14651	0	0
T87	466900	62520	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	986	986	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	475564269	35942369	0	0
DepthKnown_A	475564269	475461107	0	0
RvalidKnown_A	475564269	475461107	0	0
WreadyKnown_A	475564269	475461107	0	0
gen_passthru_fifo.paramCheckPass	986	986	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	35942369	0	0
T4	406694	19857	0	0
T5	72662	3601	0	0
T6	102091	9872	0	0
T17	220029	13641	0	0
T18	230779	14637	0	0
T34	161920	6649	0	0
T44	158702	6773	0	0
T55	134872	199230	0	0
T64	206408	11703	0	0
T87	466900	4329	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	986	986	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	475564269	32264973	0	0
DepthKnown_A	475564269	475461107	0	0
RvalidKnown_A	475564269	475461107	0	0
WreadyKnown_A	475564269	475461107	0	0
gen_passthru_fifo.paramCheckPass	986	986	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	32264973	0	0
T4	406694	19102	0	0
T5	72662	3461	0	0
T6	102091	9708	0	0
T17	220029	13258	0	0
T18	230779	14257	0	0
T34	161920	6341	0	0
T44	158702	6528	0	0
T55	134872	119427	0	0
T64	206408	11392	0	0
T87	466900	4142	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	475564269	475461107	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	986	986	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564465668	86771	0	0
DepthKnown_A	564465668	564350445	0	0
RvalidKnown_A	564465668	564350445	0	0
WreadyKnown_A	564465668	564350445	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	86771	0	0
T4	406694	78	0	0
T5	72662	18	0	0
T6	102091	68	0	0
T17	220029	151	0	0
T18	230779	151	0	0
T34	161920	69	0	0
T44	158702	30	0	0
T55	134872	34	0	0
T64	206408	94	0	0
T87	466900	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564465668	89347	0	0
DepthKnown_A	564465668	564350445	0	0
RvalidKnown_A	564465668	564350445	0	0
WreadyKnown_A	564465668	564350445	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	89347	0	0
T4	406694	78	0	0
T5	72662	18	0	0
T6	102091	68	0	0
T17	220029	151	0	0
T18	230779	151	0	0
T34	161920	69	0	0
T44	158702	30	0	0
T55	134872	34	0	0
T64	206408	94	0	0
T87	466900	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564465668	53249	0	0
DepthKnown_A	564465668	564350445	0	0
RvalidKnown_A	564465668	564350445	0	0
WreadyKnown_A	564465668	564350445	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	53249	0	0
T4	406694	75	0	0
T5	72662	17	0	0
T6	102091	67	0	0
T17	220029	95	0	0
T18	230779	95	0	0
T34	161920	68	0	0
T44	158702	28	0	0
T55	134872	5	0	0
T64	206408	90	0	0
T87	466900	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564465668	53249	0	0
DepthKnown_A	564465668	564350445	0	0
RvalidKnown_A	564465668	564350445	0	0
WreadyKnown_A	564465668	564350445	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	53249	0	0
T4	406694	75	0	0
T5	72662	17	0	0
T6	102091	67	0	0
T17	220029	95	0	0
T18	230779	95	0	0
T34	161920	68	0	0
T44	158702	28	0	0
T55	134872	5	0	0
T64	206408	90	0	0
T87	466900	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564465668	33522	0	0
DepthKnown_A	564465668	564350445	0	0
RvalidKnown_A	564465668	564350445	0	0
WreadyKnown_A	564465668	564350445	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	33522	0	0
T4	406694	3	0	0
T5	72662	1	0	0
T6	102091	1	0	0
T17	220029	56	0	0
T18	230779	56	0	0
T34	161920	1	0	0
T44	158702	2	0	0
T55	134872	29	0	0
T64	206408	4	0	0
T87	466900	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564465668	36098	0	0
DepthKnown_A	564465668	564350445	0	0
RvalidKnown_A	564465668	564350445	0	0
WreadyKnown_A	564465668	564350445	0	0
gen_passthru_fifo.paramCheckPass	2877	2877	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	36098	0	0
T4	406694	3	0	0
T5	72662	1	0	0
T6	102091	1	0	0
T17	220029	56	0	0
T18	230779	56	0	0
T34	161920	1	0	0
T44	158702	2	0	0
T55	134872	29	0	0
T64	206408	4	0	0
T87	466900	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564465668	564350445	0	0
T4	406694	406534	0	0
T5	72662	72600	0	0
T6	102091	102040	0	0
T17	220029	219913	0	0
T18	230779	230663	0	0
T34	161920	161869	0	0
T44	158702	158588	0	0
T55	134872	134866	0	0
T64	206408	206295	0	0
T87	466900	466842	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2877	2877	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T34	1	1	0	0
T44	1	1	0	0
T55	1	1	0	0
T64	1	1	0	0
T87	1	1	0	0